mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 170

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
Technical Data
NOTE:
NOTE:
Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify-write operation on the PLL control register clears the PLLF
bit.
PLLON — PLL On Bit
BCS — Base Clock Select Bit
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See
PCTL3–PCTL0 — Unimplemented
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). See
Circuit. Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM
output, CGMOUT. CGMOUT frequency is one-half the frequency of
the selected clock. BCS cannot be set while the PLLON bit is clear.
After toggling BCS, it may take up to three CGMXCLK and three
CGMVCLK cycles to complete the transition from one source clock to
the other. During the transition, CGMOUT is held in stasis. See
Base Clock Selector
the BCS bit.
These bits provide no function and always read as logic 1s.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = PLL on
0 = PLL off
1 = CGMVCLK divided by two drives CGMOUT.
0 = CGMXCLK divided by two drives CGMOUT.
Clock Generator Module (CGM)
Go to: www.freescale.com
10.4.3 Base Clock Selector
Circuit. Reset and the STOP instruction clear
10.4.3 Base Clock Selector
Circuit.
MC68HC908AS60 — Rev. 1.0
10.4.3