cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 90

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

11.2.5 External Clock Reference
Table 11-17. External Clock Reference AC Specifications
11.2.6 Phase-Locked Loop
Table 11-18. PLL DC Specifications
Table 11-19. PLL AC Specifications
Document Number: 001-44094 Rev. *J
I
Fpllin
Fpllout
Jperiod-rms Jitter (rms)
Notes
Parameter
DD
Parameter
56. Based on device characterization (Not production tested).
57. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
58. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
Parameter
PLL operating current
PLL input frequency
PLL intermediate frequency
PLL output frequency
Lock time at startup
PLL output duty cycle
External frequency range
Input duty cycle range
Input edge rate
[56]
Description
Description
Description
[57]
[57]
[58]
PRELIMINARY
In = 3 MHz, Out = 80 MHz
In = 3 MHz, Out = 24 MHz
Output of prescaler
All PLL output frequencies
Measured at V
V
IL
to V
[56]
IH
Conditions
Conditions
Conditions
DDIO
PSoC
/2
®
5: CY8C55 Family Datasheet
Min
Min
Min
24
45
0.1
30
–
–
1
1
–
–
0
Typ
400
200
Typ
Typ
50
–
–
–
–
–
–
–
–
Max
Max
250
250
Max
48
67
55
33
70
–
–
3
–
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Units
Units
Units
MHz
MHz
MHz
MHz
V/ns
µA
µA
µs
ps
%
%
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