cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 9

• Manufacturer Part Number: cy8c5588pvi-115es0
• Description: Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
• Manufacturer: Cypress Semiconductor Corporation.

3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for
high-current DACs (IDAC).
OpAmp0out, OpAmp1out, OpAmp2out, OpAmp3out. High
current output of uncommitted opamp.
Extref0, Extref1. External reference input to the analog system.
OpAmp0-, OpAmp1-, OpAmp2-, OpAmp3-. Inverting input to
uncommitted opamp.
OpAmp0+, OpAmp1+, OpAmp2+, OpAmp3+. Noninverting
input to uncommitted opamp.
GPIO. Provides interfaces to the CPU, digital peripherals,
analog peripherals, interrupts, LCD segment drive, and
CapSense.
I2C0: SCL, I2C1: SCL. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I
on an address match. Any I/O pin can be used for I
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 33-MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Provides interfaces to the CPU, digital peripherals and
interrupts with a programmable high threshold voltage, analog
comparator, high sink current, and high impedance state when
the device is unpowered.
SWDCK. SWD Clock programming and debug port connection.
SWDIO. SWD Input and Output programming and debug port
connection.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3 TRACEPORT connection, clocks
TRACEDATA pins.
TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections,
output data.
Document Number: 001-44094 Rev. *J
Notes
7. GPIOs with opamp outputs are not recommended for use with CapSense.
8. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
[7]
2
2
C SCL line providing wake from sleep
C SDA line providing wake from sleep
[7]
PRELIMINARY
2
2
C SCL if
C SDA if
SWV. SWV output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
USB.
V
V
V
Requires a 1 µF capacitor to V
external use.
V
The two V
between them as short as possible, and a 1 µF capacitor to V
see
use.
V
regulator. V
device. All other supply pins must be less than or equal to
V
V
V
V
V
V
V
V
and must be less than or equal to V
with V
should be tied to ground (V
XRES (and configurable XRES). External reset pin. Active low
with internal pull-up. In 48-pin SSOP parts, P1[2] may be
configured as XRES. In all other parts the pin is configured as a
GPIO.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C55 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low-power 32-bit three-stage pipelined
Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
BOOST
BAT
CCA
CCD
DDA
DDA
DDD
DDD
SSA
SSB
SSD
DDIO0
DDIO
PSoC
Power System on page
. Battery supply to boost pump.
. Ground for all analog peripherals.
. Ground connection for boost pump.
. Ground for all digital logic and I/O pins.
[8]
[8]
. Output of analog core regulator and input to analog core.
. Output of digital core regulator and input to digital core.
. Supply for all analog peripherals and analog core
.
. Supply for all digital peripherals and digital core regulator.
must be less than or equal to V
DDIO0
must be tied to a valid operating voltage (1.71 V to 5.5 V),
, V
. Power sense connection to boost pump.
DDIO1
CCD
DDIO
DDIO
DDA
, V
®
DDIO2
pins must be shorted together, with the trace
, V
. Pins are No Connect (NC) on devices without
. Pins are No Connect (NC) on devices without
5: CY8C55 Family Datasheet
must be the highest voltage present on the
DDIO2
or V
, V
DDIO3
DDIO3
SSD
20. Regulator output not for external
SSA
are not used then that V
or V
. Supply for I/O pins. Each
DDA
. Regulator output not for
SSA
DDA
. If the I/O pins associated
).
.
DDD
DDD
Page 9 of 102
DDIO
instead
instead
SSD
;
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