cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 71

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cy8c5588pvi-115es0

Manufacturer Part Number
cy8c5588pvi-115es0
Description
Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
11.0.5 IDAC
Table 11-7. IDAC (Current Digital-to-Analog Converter) DC Specifications
Table 11-8. IDAC (Current Digital-to-Analog Converter) AC Specifications
11.0.6 VDAC
Table 11-9. VDAC (Voltage Digital-to-Analog Converter) DC Specifications
Document Number: 001-44094 Rev. *J
Resolution
I
INL
DNL
Ezs
Eg
IDAC_ICC
IDAC_ICC
F
T
Resolution
R
V
INL
DNL
Ezs
Eg
VDAC_ICC
VDAC_ICC
Note
OUT
39. Based on device characterization (Not production tested).
SETTLE
DAC
OUT
OUT
Parameter
Parameter
Parameter
Output current
Integral non linearity
Differential non linearity
Zero scale error
Gain error
DAC current low speed mode
DAC current high speed mode
Update rate
Settling time to 0.5LSB
Fast mode
Slow mode
Output resistance
Output voltage range
Integral non linearity
Differential non linearity
Zero scale error
Gain error
DAC current low speed mode
DAC current high speed mode
High
Medium
Low
High
Low
High
Low
[39]
[39]
[39]
Description
Description
Description
[39]
[39]
PRELIMINARY
[39]
[39]
[39]
[39]
Code = 255, V
600 
Code = 255, V
300 
Code = 255, RL 600 
Code = 255, RL 600 
RL 600 , CL=15 pF
RL 600 , CL=15 pF
Uncompensated
Temperature compensated
Code = 0
Code = 0
Full scale transition, 600  load, 
CL = 15 pF
Independent of IDAC range setting
(I
Independent of IDAC range setting
(I
V
V
Code = 255, V
Code = 255
CL=15 pF
CL=15 pF
Uncompensated
Temperature compensated
Code = 0
Code = 0
OUT
OUT
OUT
OUT
)
)
= 4 V
= 1 V
Conditions
Conditions
Conditions
DDA
DDA
DDA
PSoC
 2.7 V, RL
 2.7 V, RL
> 5 V
®
5: CY8C55 Family Datasheet
Min
Min
Min
31.875
2.040
2.040
Typ
255
Typ
Typ
16
8
0
8
4
4
1
1000
TBD
TBD
Max
Max
Max
±
100
500
100
100
500
3.5
±
0.5
±
±
±
±
8
3
1
1
1
1
1
Page 71 of 102
Units
Units
Msps
Units
LSB
LSB
LSB
LSB
LSB
LSB
mA
mA
µA
µA
µA
µA
k
k
µA
µA
ns
ns
%
%
%
%
V
V
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