cy8c5588pvi-115es0 Cypress Semiconductor Corporation., cy8c5588pvi-115es0 Datasheet - Page 27
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cy8c5588pvi-115es0
Manufacturer Part Number
cy8c5588pvi-115es0
Description
Cy8c55 Family Data Sheet Programmable System-on-chip Psoc?
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CY8C5588PVI-115ES0.pdf
(102 pages)
- Current page: 27 of 102
- Download datasheet (3Mb)
Document Number: 001-44094 Rev. *J
Digital Input Path
Digital Output Path
Digital Input Path
Digital Output Path
PRT[x]DR
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
Digital System Output
PRT[x]BYP
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Pin Interrupt Signal
PICU[x]INTSTAT
USBIO_CR1[4,5]
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
PRT[x]SYNC_OUT
USBIO_CR1[7]
USB SIE Control for USB Mode
Digital System Output
PRT[x]BYP
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
Pin Interrupt Signal
PICU[x]INTSTAT
Figure 6-4. SIO Input/Output Block Diagram
PRELIMINARY
Figure 6-5. USBIO Block Diagram
0
1
0
1
Interrupt
Interrupt
Logic
Logic
Thresholds
In
OE
USB or I/O
In
D+ 1.5 k
D+D- 5 k
Open Drain
Drive
Logic
Buffer
Drive
Logic
Input Buffer Disable
PSoC
Slew
Cntl
Vddd
®
Vddd
5 k
Naming Convention
5: CY8C55 Family Datasheet
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Driver
Vhigh
D+ pin only
‘x’ = Port Number
‘y’ = Pin Number
1.5 k
Vddd
Vddd
PIN
PIN
Page 27 of 102
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