pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 751

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

1. Introduction
2. Functional Description
2.1.1 Test Access Port (TAP)
1.1 Features
2.1 General Operations
The TM5250 Debug (TM_DBG) interface consists of the Test Access Port (TAP), the
TAP Controller, a JTAG Instruction register and internal debug registers. The TAP
controller from which the TM_DBG module receives its commands resides in the test
control block, which also facilitates boundary scanning and other DFT features.
The TM_DBG has registers that can be programmed for control and communication
with an on-chip TriMedia TM5250 CPU.
The Test Access Port (TAP) includes four dedicated input pins and one output pin:
TCK provides the clock for test logic required by the JTAG standard. TCK is
asynchronous to any system clock. Stored state devices in the JTAG controller will
retain their state indefinitely when TCK is stopped at 0 or 1.
The signal received at TMS is decoded by the TAP controller to control test functions.
The test logic is required to sample TMS at the rising edge of TCK.
Serial test instructions and test data are received at TDI. The TDI signal is required to
be sampled at the rising edge of TCK. When test data is shifted from TDI to TDO, the
data must appear without inversion at TDO after a number of rising and falling edges
of TCK determined by the length of the instruction or test data register selected.
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Chapter 24: TM5250 Debug
PNX17xx Series Data Book – Volume 1 of 1
Rev. 1 — 17 March 2006
TCK (Test Clock)
TMS (Test Mode Select)
TDI (Test Data In)
TDO (Test Data Out)
Preliminary data sheet