pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 327

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 6:
logical
address
Address Mapping: Interleaved Mode
2.3.1 Memory Region Mapping Scheme
2.3 Addressing
ROW_WIDTH
row
It should also be noted that under some circumstances the PMAN will be granted a
request even though there is a valid CPU request pending. This can only be detected
within simulations and will be very difficult for a user to actually discern. This
condition results from the particular optimizations that were performed on the logic
and only delays a CPU by one DDR transaction. The overall bandwidth for the CPU is
not affected.
The DDR SDRAM Controller performs address mapping of MTL addresses onto DDR
memory rank, bank, row and column addresses. The 32-bit MTL addresses, provided
to the DDR controller, cover a 4-GB address range. Of these 32-bit addresses, the
upper four bits are ignored by the DDR controller, reducing the addressable range to
256 MB. Note that the DDR controller only supports up to 256 MB of DDR memory
(either implemented by a single rank or two ranks of size 128 MB).
For a 32-bit DDR interface, each column is 4 bytes wide. Therefore the 2 least
significant bits of the MTL address are ignored.
For a 16-bit DDR interface (or a 32-bit DDR interface using the half width mode),
each column is 2 bytes wide. Therefore the least significant bit of the MTL address is
ignored.
The mapping is defined by the MMIO register DDR_DEF_BANK_SWITCH.
2^BANK_SWITCH defines the size of the interleaving. The addressing is then done
as pictured in
Changing the BANK_SWITCH value may improve/decrease performance. This is
application specific. 32-byte and 1024-byte are the recommended operating modes.
This mapping can be illustrated in the following tables. In all of these examples a 32-
bit DDR interface and a DDR burst length of 8 32-bit/4-byte elements (a full DDR
burst transfers 8 * 4 bytes= 32 bytes).
COLUMN_WIDTH -
BANK_SWITCH
column
Figure
Rev. 1 — 17 March 2006
6.
2^(COLUMN_WIDTH - BANK_SWITCH)
bank
2
r = 2^ROW_WIDTH
BANK_SWITCH
column
ROW r-1
BANK 0
BANK 0
BANK 0
BANK 0
ROW 2
ROW 1
ROW 0
least significant bit is:
bit 0 for x8
bit 1 for x16
bit 2 for x32
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2^BANK_SWITCH columns
ROW r-1
BANK 1
BANK 1
BANK 1
BANK 1
ROW 2
ROW 1
ROW 0
Chapter 9: DDR Controller
PNX17xx Series
ROW r-1
BANK 2
BANK 2
BANK 2
BANK 2
ROW 2
ROW 1
ROW 0
ROW r-1
BANK 3
BANK 3
BANK 3
BANK 3
ROW 2
ROW 1
ROW 0
9-10