pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 136

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: Miscellaneous System MMIO registers
PNX17XX_SER_1
Preliminary data sheet
System Registers
Offset 0x06 3050
31:2
1
0
Offset 0x06 3500
31:0
Offset 0x06 3504
31:0
Offset 0x06 3508
31:0
Offset 0x06 350C
31:0
Offset 0x06 3510
31:0
Offset 0x06 3514
31:0
Offset 0x06 3518
31:0
Offset 0x06 351C
31:0
Bit
Symbol
Unused
PCI_INTA
PCI_INTA_OE
SCRATCH0
SCRATCH1
SCRATCH2
SCRATCH3
SCRATCH4
SCRATCH5
SCRATCH6
SCRATCH7
8.1 Miscellaneous System MMIO registers
PCI_INTA
SCRATCH0
SCRATCH1
SCRATCH2
SCRATCH3
SCRATCH4
SCRATCH5
SCRATCH6
SCRATCH7
Acces
s
-
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
-
0x1
0x0
-
-
-
-
-
-
-
-
Rev. 1 — 17 March 2006
Description
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Writes PCI_INTA_N pin value if PCI_INTA_OE is enabled
To read the PCI_INTA_N pin value use IPENDING MMIO register.
Enable of PCI_INTA_N output
Note: In order to operate the PCI_INTA_N pin as an open drain pin
as required by the PCI specification, the software must enable the
output only when driving a ‘0’, i.e. asserting an interrupt.
Note: In order to avoid a race condition between the data and the
enable or glitches on the PCI_INTA_N pin, the enable should only
be changed once the data is stable.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
32-bit writable and readable register. Not cleared at reset for debug
purposes.
0: PCI_INTA_N is 0 (asserted)
1: PCI_INTA_N is 1 (de-asserted)
0: Disable PCI_INTA_N output
1: Enable PCI_INTA_N output
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
3-27