pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 489
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pnx1700
Manufacturer Part Number
pnx1700
Description
Connected Media Processor
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1700.pdf
(832 pages)
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Philips Semiconductors
Volume 1 of 1
PNX17XX_SER_1
Preliminary data sheet
Figure 1:
MMIO/DCS Bus
Top Level Block Diagram
VDI Pads
32
1.1 FGPI Overview
Refer to
module to the MMIO and MTL Busses within the PNX17xx Series. All external FGPI
signals are registered and routed through the Input Router module before being
presented to the FPGI module. Latency buffering of data and endian conversion is
done in the MTL DTL Adapter. All FGPI register access is through the MMIO DTL
adapter.
Input Router
Clock Block
Figure
1. This block diagram shows the top level connection of the FGPI
32
Rev. 1 — 17 March 2006
32
Chapter 14: FGPI: Fast General Purpose Interface
32
32
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
64
MTL Bus
14-2
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