pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 648

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 30: EngineStatus
PNX17XX_SER_1
Preliminary data sheet
Bit
Drawing Engine Real Time Registers
Offset 0x04 F800
31:11
10
9
8
7:4
3
2
1
0
Symbol
Reserved
IRQ
DEDone
DEBusy
Reserved
HFIFO_not empty
HFIFO_full
Vector active
BLT active
EngineStatus
This register holds the background color for monochrome pattern expansion, lines,
and solid fills. The appropriate number of bytes need to be loaded in accordance with
the current color depth. Thus, if the current depth is 8 bits, only the lowest byte need
be written. If the depth is 16 bits, the lowest two bytes need to be written.
When reading the value of this register, the lower byte will be replicated into all four
byte lanes in 8-bpp mode. In 16-bpp mode, the lower word will be replicated into the
upper word. In 32-bit mode, all bits are unique and will read back the 32-bit data that
was written. This register is unchanged by drawing operations.
This read-only register returns the drawing engine status. Writes to this register have
no effect but do not hang the bus.
Acces
s
R
R
R
R
R
R
R
Value
0
1
0
0
0
0
0
Rev. 1 — 17 March 2006
Description
Draw Engine interrupt request status
1 = A 2D interrupt is being requested. This reflects the actual state
of the IRQ signal leaving the Drawing Engine.
DeDone and DEBusy are the primary Drawing Engine activity
indicators.They are the complement of each other.
When DEBusy is logic 1 (DEDone a 0), the Drawing Engine is
active. If EngineConfig bit 9 is a 1, “active” is defined as:
processing a register access
emptying commands or data from the Host FIFO
performing an operation such as a bitblt or bitblt line
waiting for a memory transaction to complete
If EngineConfig bit 9 is a 0, the engine is active when a blt/vector
starts and becomes inactive when the blt/vector finishes. All
memory writes are complete, AND the host FIFO is empty. DEBusy
is read as logic 0, the Drawing Engine is guaranteed to be idle.
Host FIFO is not empty.
Host FIFO is full. BLT is busy; another BLT is pending in shadow
registers.
Vector is in process.
BLT is in process.
Chapter 20: 2D Drawing Engine
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
20-28