pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 589

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 3: De-Interlacing Mode Maximum Filter Lengths
PNX17XX_SER_1
Preliminary data sheet
Input Format
4:2:0 or 4:2:2 planar
4:2:0 or 4:2:2 semi-planar
4:2:2 single plane
1
Only supported in Vertical-First mode
2.4.1 Task Control
2.4 General Operations
EDDI
Yes
Yes
No
This section provides the details on how the MBS functions. A description of each
functional group is provided.
Since the MBS is capable of processing several video streams in sequence, a
pipelining mechanism is implemented for scaling a sequence of tasks. A task is
described by a data structure stored in memory. Writing the base address of this task
into the Task FIFO schedules the task to be executed after the completion
(processing) of the previously-scheduled tasks.
In addition to the task list in the FIFO, each Task structure in memory can consist of a
linked list of sub tasks that will be executed in sequence ( e.g. , HD scaling task via
partitioning). The software scheduling algorithm is responsible for preventing the Task
FIFO from overflowing. An interrupt can be generated, once the last task in the FIFO
gets executed, in order to request new tasks from the scheduler. Other interrupt
events also exist and they aid in the task of keeping the task FIFO filled and avoiding
overflow in the four available FIFO slots.
Figure 5:
MSA 2 Field (Y:UV Taps)
6:6
6:6
Not supported
Task FIFO and Linked List
FIFO out
Rev. 1 — 17 March 2006
FIFO in
Base 2
Base 1
empty
empty
MSA 3 Field (Y:UV Taps)
Not supported
6:6
Not supported
1
Chapter 19: Memory Based Scaler
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX17xx Series
Descriptor #2 start
Descriptor #1 start
Descriptor #2 end
Descriptor #1 end
Memory
Sub-Task Base
Sub-Task start
Median (Y:UV Taps)
6:6
6:6
6:6
...
...
...
19-6