pnx1700 NXP Semiconductors, pnx1700 Datasheet - Page 246

• Manufacturer Part Number: pnx1700
• Description: Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 9: Registers Description
PNX17XX_SER_1
Preliminary data sheet
Bit
20:18
17
16
15
14:12
11
10
9:7
6:2
1
0
Offset 0x04 0014
31:20
19
18
Symbol
base18_siz
en_base18
base14_prefetchable
Reserved
base14_siz
en_base14
base10_prefetchable
base10_siz
Reserved
en_config_manag
en_pci_arb
Reserved
decouple_targ
fst_retry
PCI Control
Acces
s
R/W1
R/W1
R/W1
R
R/W1
R/W1
R/W1
R/W1
R/W1
R/W1
R
R/W
R/W
Value
011
1
0
0
000
1
1
100
1
0
0
0
0
Rev. 1 — 17 March 2006
Description
The size of aperture located by PCI cfg base18 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
111 = 256 MB
This aperture is used as the XIO aperture in the PNX17xx Series.
Note: If expanding to 128 MB, the default setting of base18 address
will overlap with the default base14 address. To avoid an address
conflict, the base18 address or the base14 address should be
relocated before setting the base18_siz.
Enable 3rd aperture, PCI base address 18. The PNX17xx Series
will always use this aperture.
PCI Base address 14 is a non-prefetchable memory aperture.
The size of aperture located by PCI cfg base 14 is 000 = 2 MB.
This aperture is used as the MMIO aperture in the PNX17xx Series.
Enable 2nd aperture, PCI base address 14. The PNX17xx Series
will always use this aperture.
PCI Base address 10 is a prefetchable memory aperture.
The size of aperture located by PCI cfg base 10 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
111 = 256 MB
This aperture is used as the DRAM aperture in the PNX17xx
Series.
Enable configuration management.
Enable internal PCI system arbitration.
0 = Use strict order rules on writes to internal targets. Memory
writes will complete before accepting writes to DCS. Writes to DCS
will complete before accepting writes to memory.
1 = Relax above order rule. Allow writes to be processed as long as
target path is not full.
0 = All reads will wait for up to 16 PCI clocks before terminating the
transaction. If data is not ready by this time, the transaction will end
with RETRY.
1 = The initial read from memory (BAR0) will terminate with a
RETRY within 2 PCI clocks. Subsequent reads will wait for up to 16
/ 8 PCI clocks
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX17xx Series
7-25