dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 83

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
INSTRUCTION
OPERATIONS
AT ADDRESS
AT ADDRESS
EXECUTION
X MEMORY
Y MEMORY
(DATA ALU)
PARALLEL
ADDRESS
INSTRUCTION EXECUTION
UPDATE
INSTRUCTION DECODE
(AGU)
$0005
$0006
$0007
$0008
$0009
Instruction/Data Fetch
Instruction Decode
Instruction Execution
INSTRUCTION FETCH
SERIAL EXECUTION OF INSTRUCTIONS
A:
A2=$00
A1=$000066
A0=$000000
X0=$400000
Y1=$000077
CONDITIONS
R0=$0005
R4=$0008
$000005
$000006
$000007
$000008
$000009
INITIAL
PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
DATA
DATA
Instruction Cycle 1
INSTRUCTION
Instruction 1
Instruction 2
Instruction 3
Freescale Semiconductor, Inc.
FETCH
LOGIC
For More Information On This Product,
Instruction Cycle 1 Instruction Cycle 2 Instruction Cycle 3 Instruction Cycle 4 Instruction Cycle 5
Figure 5-3 Three-Stage Pipeline
PROGRAM CONTROL UNIT
1
I1
MACR
CLR
MAC
EXECUTION OF EXAMPLE PROGRAM
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EXAMPLE PROGRAM SEGMENT
Instruction Cycle 2
SEQUENCE OF OPERATIONS
INSTRUCTION
INSTRUCTION
DECODE
FETCH
LOGIC
LOGIC
X0,Y1,A
A
X0,Y1,A
I2
I1
2
1
Instruction Cycle 3
X:(R0)+,X0
X0,X:(R0)+
X:(R0)+,X0
INSTRUCTION
INSTRUCTION
INSTRUCTION
EXECUTION
DECODE
LOGIC
FETCH
LOGIC
LOGIC
A:
A2=$00
A1=$0000A2
A0=$000000
X0=$000005
Y1=$000008
$000005
$000006
$000007
$000008
$000009
R0=5+1
R4=8+1
I3
I2
I1
2
1
3
Y:(R4)+,Y1
A,Y:(R4)-
Y:(R4)+,Y1
Instruction Cycle
INSTRUCTION
INSTRUCTION
INSTRUCTION
EXECUTION
DECODE
A:
A2=$00
A1=$000000
A0=$000000
X0=$000005
Y1=$000008
LOGIC
FETCH
LOGIC
LOGIC
$0000A2
R0=6+1
R4=9–1
$000005
$000005
$000007
$000008
I4
I3
I2
2
4
3
Instruction Cycle 5
INSTRUCTION
INSTRUCTION
INSTRUCTION
EXECUTION
A:
A2=$00
A1=$000000
A0=$000050
X0=$000007
Y1=$000008
DECODE
LOGIC
FETCH
LOGIC
LOGIC
$000005
$000005
$000007
$0000A2
$000008
R0=7+1
R4=8+1
I5
I4
I3
5 - 7
3
5
4