dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 389
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dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
- Current page: 389 of 637
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specified in the effective address field is always updated independently of the state of the
n
source operand S. Absolute short and I/O short addressing modes may also be used .
Restrictions: A JSCLR instruction used within a DO loop cannot specify the loop
address (LA) as its target.
A JSCLR located at LA, LA–1, or LA–2 of a DO loop, cannot specify the program control-
ler registers SR, SP, SSH, SSL, LA, or LC as its target.
JSCLR SSH or JSCLR SSL cannot follow an instruction that changes the SP.
A JSCLR instruction cannot be repeated using the REP instruction.
Example:
Explanation of Example: In this example, program execution is transferred to the sub-
routine at absolute address P:$1357 in program memory if bit 1 of the external I/O loca-
tion Y:<<$FFE3 is a zero. If the specified bit is not clear, no jump is taken and the
program counter (PC) is incremented by 1.
MOTOROLA
JSCLR
th
JSCLR #$1,Y:<<$FFE3,$1357
bit. All address register indirect addressing modes may be used to reference the
:
:
Freescale Semiconductor, Inc.
For More Information On This Product,
Jump to Subroutine if Bit Clear
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
;go sub. at P:$1357 if bit 1 in Y:$FFE3 is clear
JSCLR
A - 123
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