dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 296

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Add the source operand S to one-half the destination operand D and store
the result in the destination accumulator. The destination operand D is arithmetically
shifted one bit to the right while the MS bit of D is held constant prior to the addition oper-
ation. In contrast to the ADDL instruction, the carry bit is always set correctly, and the
overflow bit can only be set by the addition operation and not by an overflow due to the
initial shifting operation. This instruction is useful for efficient divide and decimation in
time (DIT) FFT algorithms.
Example:
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the
value $80:000000:2468AC, and the 56-bit B accumulator contains the value
$00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accu-
mulator to the value in the B accumulator and stores the 56-bit result in the A accumula-
tor.
A - 30
ADDR
ADDR B,A X0,X:(R1)+N1 Y0,Y:(R4)–
S+D / 2 D (parallel move)
:
:
A
B
$00:013570:000000
$80:000000:2468AC
Before Execution
Freescale Semiconductor, Inc.
For More Information On This Product,
INSTRUCTION DESCRIPTIONS
Shift Right and Add Accumulators
INSTRUCTION SET DETAILS
Go to: www.freescale.com
Assembler Syntax:
A
B
;B+A / 2 A, save X0 and Y0
ADDR S,D (parallel move)
$00:013570:000000
$C0:013570:123456
After Execution
ADDR
MOTOROLA