dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 283

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Note that the signed integer portion of an accumulator IS NOT necessarily the same as
the extension register portion of that accumulator. The signed integer portion of an accu-
mulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling
mode being used. The extension register portion of an accumulator (A2 or B2) is always the
MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accu-
mulator and NOT the extension register portion of that accumulator. For example, if
the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of
the A or B accumulator consists of bits 47 through 55. If the A accumulator contained the
signed 56-bit value $00:800000:000000 as a result of a data ALU operation, the E bit
would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., nei-
ther 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is
specified as a source operand in a move-type operation. This limiting operation will result in
either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified
destination. The only situation in which the signed integer portion of an accumulator and
the extension register portion of an accumulator are the same is in the “Scale Down” scaling
mode (i.e., S1=0 and S0=1).
U (Unnormalized Bit)
N (Negative Bit)
Z (Zero Bit)
V (Overflow Bit)
MOTOROLA
Freescale Semiconductor, Inc.
S1
0
0
1
Set if the two MS bits of the MSP portion of the A or B result are the
same. Cleared otherwise. The MSP portion is defined by the scal-
ing mode. The U bit is computed as follows:
S1
0
0
1
Set if the MS bit 55 of the A or B result is set. Cleared otherwise.
Set if the A or B result equals zero. Cleared otherwise.
Set if an arithmetic overflow occurs in the 56-bit A or B result. This
indicates that the result cannot be represented in the 56-bit accu-
mulator; thus, the accumulator has overflowed. Cleared otherwise.
For More Information On This Product,
CONDITION CODE COMPUTATION
INSTRUCTION SET DETAILS
S0
0
1
0
S0
0
1
0
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Scaling Mode
No Scaling
Scale Down
Scale Up
Scaling Mode
No Scaling
Scale Down
Scale Up
Signed Integer Portion
Bits 55, 54, . . . . 48, 47
Bits 55, 54, . . . . 49, 48
Bits 55, 54, . . . . 47, 46
U Bit Computation
U=(Bit 47
U=(Bit 48
U=(Bit 46
Bit 46)
Bit 47)
Bit 45)
A - 17