dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 546

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Subtract the source operand S from one-half the destination operand D
and store the result in the destination accumulator. The destination operand D is arith-
metically shifted one bit to the right while the MS bit of D is held constant prior to the sub-
traction operation. In contrast to the SUBL instruction, the carry bit is always set
correctly, and the overflow bit can only be set by the subtraction operation, and not by an
overflow due to the initial shifting operation. This instruction is useful for efficient divide
and decimation in time (DIT) FFT algorithms.
Example:
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the
value $80:000000:2468AC, and the 56-bit B accumulator contains the value
$00:000000:123456. The SUBR B,A instruction subtracts the value in the B accumulator
from one-half the value in the A accumulator and stores the 56-bit result in the A accu-
mulator.
A - 280
SUBR
D/2–S
SUBR B,A N5,Y:–(R5)
A
B
:
:
D (parallel move)
$80:000000:2468AC
$00:000000:123456
Before Execution
Freescale Semiconductor, Inc.
Shift Right and Subtract Accumulators
For More Information On This Product,
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
;A/2–B
Assembler Syntax:
A
B
A, update R5, save N5
SUBR S,D (parallel move)
$C0:000000:000000
$00:000000:123456
After Execution
SUBR
MOTOROLA