dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 542

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Subtract the source operand S from the destination operand D and store
the result in the destination operand D. Words (24 bits), long words (48 bits), and accu-
mulators (56 bits) may be subtracted from the destination accumulator.
Note: The carry bit is set correctly using word or long-word source operands if the exten-
sion register of the destination accumulator (A2 or B2) is the sign extension of bit 47 of
the destination accumulator (A or B). The carry bit is always set correctly using accumu-
lator source operands.
Example:
Explanation of Example: Prior to execution, the 24-bit X1 register contains the value
$000003, and the 56-bit A accumulator contains the value $00:000058:242424. The
SUB instruction automatically appends the 24-bit value in the X1 register with 24 LS
zeros, sign extends the resulting 48-bit long word to 56 bits, and subtracts the result from
the 56-bit A accumulator. Thus, 24-bit operands are subtracted from the MSP portion of
A or B (A1 or B1) because all arithmetic instructions assume a fractional, twos comple-
ment data representation. Note that 24-bit operands can be subtracted from the LSP por-
tion of A or B (A0 or B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit
word by loading X1 or Y1 with the sign extension of X0 or Y0, and executing a SUB X,A
or SUB Y,A instruction.
A - 276
SUB
D–S
SUB X1,A X:(R2)+N2,R0
X1
A
D (parallel move)
:
:
$00:000058:242424
Before Execution
Freescale Semiconductor, Inc.
For More Information On This Product,
$000003
INSTRUCTION DESCRIPTIONS
INSTRUCTION SET DETAILS
Go to: www.freescale.com
Subtract
;24-bit subtract, load R0, update R2
Assembler Syntax:
X1
A
SUB S,D (parallel move)
$00:000055:242424
After Execution
$000003
MOTOROLA
SUB