dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 385
dsp56000
Manufacturer Part Number
dsp56000
Description
24-bit Digital Signal Processor Family Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56000.pdf
(637 pages)
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where
U denotes the logical complement of U,
Restrictions: A JScc instruction used within a DO loop cannot specify the loop
address (LA) as its target.
A JScc instruction used within in a DO loop cannot begin at the address LA within that
DO loop.
A JScc instruction cannot be repeated using the REP instruction.
Example:
Explanation of Example: In this example, program execution is transferred to the sub-
routine at address P:(R3+N3) in program memory if the limit bit is set (L=1). Both the
return address (PC) and the status register (SR) are pushed onto the system stack prior
to transferring program control to the subroutine if the specified condition is true. If the
specified condition is not true, no jump is taken and the program counter is incremented
by 1.
Condition Codes:
The condition codes are not affected by this instruction.
MOTOROLA
JScc
denotes the logical AND operator, and
denotes the logical OR operator,
denotes the logical Exclusive OR operator
JSLS (R3+N3)
15
LF
:
:
DM
14
13
T
Freescale Semiconductor, Inc.
**
12
For More Information On This Product,
MR
Jump to Subroutine Conditionally
INSTRUCTION DESCRIPTIONS
S1
11
INSTRUCTION SET DETAILS
S0
10
Go to: www.freescale.com
;jump to subroutine at P:(R3+N3) if limit set (L=1)
I1
9
I0
8
S
7
6
L
E
5
U
4
CCR
N
3
Z
2
V
1
C
0
JScc
A - 119
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