dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 510

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

Operation:
Description: Logically inclusive OR the source operand S with bits 47–24 of the destina-
tion operand D and store the result in bits 47–24 of the destination accumulator. This
instruction is a 24-bit operation. The remaining bits of the destination operand D are not
affected.
Example:
Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value
$FF0000, and the 56-bit B accumulator contains the value $00:123456:789ABC. The OR
Y1,B instruction logically ORs the 24-bit value in the Y1 register with bits 47–24 of the B
accumulator (B1) and stores the result in the B accumulator with bits 55–48 and 23–0
unchanged.
Condition Codes:
S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION
L — Set if data limiting has occurred during parallel move
N — Set if bit 47 of A or B result is set
Z — Set if bits 47-24 of A or B result are zero
V — Always cleared
A - 244
OR
S+D[47:24]
where + denotes the logical inclusive OR operator
OR Y1,B1
Y1
B
LF
1
5
:
:
DM
14
$00:123456:789ABC
Before Execution
D[47:24] (parallel move)
13
T
Freescale Semiconductor, Inc.
**
BA,L:$1234
12
For More Information On This Product,
MR
$FF0000
INSTRUCTION DESCRIPTIONS
S1
11
INSTRUCTION SET DETAILS
S0
10
Go to: www.freescale.com
Logical Inclusive OR
I1
9
I0
8
S
7
Assembler Syntax:
;save A1,B1, OR Y1 with B
Y1
B
L
6
E
5
OR
$00:FF3456:789ABC
After Execution
U
4
CCR
N
3
S,D (parallel move)
$FF0000
Z
2
V
1
C
0
MOTOROLA
OR