dsp56000 Freescale Semiconductor, Inc, dsp56000 Datasheet - Page 188

• Manufacturer Part Number: dsp56000
• Description: 24-bit Digital Signal Processor Family Manual
• Manufacturer: Freescale Semiconductor, Inc

9.4.3
9.4.4
Changes to the MF0-MF11 bits cause the following to occur:
9.4.5
Changes to the DF0-DF3 bits do not cause a loss of lock condition. The internal clocks
will immediately revert to the frequency prescribed by the new divide factor. For MF 4,
changing DF0-DF3 may lengthen the instruction cycle or CKOUT pulse following the PLL
control register update in order to keep synchronization between EXTAL and the internal
9 - 12
4. For all input frequencies which would result in a VCO output frequency lower
5. The CKP pin only affects the CKOUT clock polarity during the hardware reset
1. If the PLL is disabled, the PLOCK pin is asserted.
2. If the PLL is disabled, the internal chip clock and CKOUT are driven from the
1. The PLL will lose the lock condition, the PLOCK pin will be deasserted.
2. The PLL acquires the proper phase/frequency. Until this occurs the internal
3. When lock occurs, PLOCK is asserted and the PLL drives the internal chip
4. While PLL has not locked, CKOUT is held low if CKP is cleared. CKOUT is
Operation with PLL Disabled
Changing the MF0-MF11 Bits
Change of DF0-DF3 Bits
than the minimum specified in the device’s Technical Data Sheet (typically 10
MHz), PINIT must be cleared during hardware reset, disabling PLL operation.
Otherwise, proper operation of the PLL cannot be guaranteed. If the resulting
VCO clock frequency would be less than the minimum and the user wishes to
operate with the PLL enabled, the user must issue an instruction which loads
the PCTL control register with a multiplication factor that would bring the VCO
frequency above 10 MHz and would enable the PLL operation. Until this
instruction is executed, the PLL is disabled, which may cause a large skew
(<15nsec) between the external input clock and the internal processor clock. If
internal low frequency of operation is desired with the PLL enabled, the VCO
output frequency may be divided down by using the internal low power divider.
state. At the end of the hardware reset state, the CKP state is internally
latched.
EXTAL input.
chip clock phases will be frozen. This ensures that the clock used by the chip
is a clock that has reached a stable frequency.
clock and CKOUT.
held high if CKP is set.
Freescale Semiconductor, Inc.
PLL OPERATION CONSIDERATIONS
For More Information On This Product,
PLL CLOCK OSCILLATOR
Go to: www.freescale.com
MOTOROLA