adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 7

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

9.0 Ball Descriptions and Equivalent Circuits
Ball No.
N1/M1
V2/W1
U2/V1
H1/J1
DCLK_RST+/-
VinQ+/-
CLK+/-
VinI+/-
Name
TABLE 1. Analog Front-End and Clock Balls
Equivalent Circuit
7
Description
Differential signal I- and Q-inputs. In the Non-Du-
al Edge Sampling (Non-DES) Mode, each I- and
Q-input is sampled and converted by its respec-
tive channel with each positive transition of the
CLK input. In Non-ECM (Non-Extended Control
Mode) and DES Mode, both channels sample the
I-input. In Extended Control Mode (ECM), the Q-
input may optionally be selected for conversion
in DES Mode by the DEQ Bit (Addr: 0h, Bit 6).
Each I- and Q-channel input has an internal com-
mon mode bias that is disabled when DC-cou-
pled Mode is selected. Both inputs must be either
AC- or DC-coupled. The coupling mode is se-
lected by the V
In Non-ECM, the full-scale range of these inputs
is determined by the FSR Pin; both I- and Q-
channels have the same full-scale input range. In
ECM, the full-scale input range of the I- and Q-
channel inputs may be independently set via the
Control Register (Addr: 3h and Addr: Bh). Note
that the high and low full-scale input range setting
in Non-ECM corresponds to the mid and mini-
mum full-scale input range in ECM.
The input offset may also be adjusted in ECM.
Differential Converter Sampling Clock. In the
Non-DES Mode, the analog inputs are sampled
on the positive transitions of this clock signal. In
the DES Mode, the selected input is sampled on
both transitions of this clock. This clock must be
AC-coupled.
Differential DCLK Reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D800/500RFs in
order to synchronize them with other
ADC12D800/500RFs in the system. DCLKI and
DCLKQ are always in phase with each other,
unless one channel is powered down, and do not
require a pulse from DCLK_RST to become
synchronized. The pulse applied here must meet
timing relationships with respect to the CLK input.
Although supported, this feature has been
superseded by AutoSync.
CMO
Pin.
(Note
18)
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