adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 46

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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may be used to synchronize the Master ADC12D800/500RFs
to each other.
If the AutoSync or DCLK Reset feature is not used, see
26
In order to synchronize the DCLK (and Data) outputs of mul-
tiple ADCs, the DCLKs must transition at the same time, as
well as be in phase with one another. The DCLK at each ADC
is generated from the CLK after some latency, plus t
t
time, the CLK signal must reach each ADC at the same time.
To tune out any differences in the CLK path to each ADC, the
t
feature will also affect when the DCLK is produced at the out-
put. If the device is in Demux Mode, then there are four
possible phases which each DCLK may be generated on be-
cause the typical CLK = 1GHz and DCLK = 250 MHz for this
case. The RCLK signal controls the phase of the DCLK, so
that each Slave DCLK is on the same phase as the Master
DCLK.
The AutoSync feature may only be used via the Control Reg-
isters. For more information, see AN-2132.
17.4.2 DCLK Reset Feature
The DCLK reset feature is available via ECM, but it is disabled
by default. DCLKI and DCLKQ are always synchronized, by
design, and do not require a pulse from DCLK_RST to be-
come synchronized.
The DCLK_RST signal must observe certain timing require-
ments, which are shown in
The DCLK_RST pulse must be of a minimum width and its
deassertion edge must observe setup and hold times with re-
spect to the CLK input rising edge. These timing specifica-
tions are listed as t
14.
The DCLK_RST signal can be asserted asynchronously to
the input clock. If DCLK_RST is asserted, the DCLK output is
AD
AD
. Therefore, in order for the DCLKs to transition at the same
for recommendations about terminating unused pins.
TABLE 26. Unused AutoSync and DCLK Reset Pin
adjust feature may be used. However, using the t
DCLK_RST+
DCLK_RST-
RCOUT1+/-
RCOUT2+/-
RCLK+/-
Pin(s)
PWR
Recommendation
, t
Connect to GND via 1kΩ resistor.
SR
Connect to V
and t
Figure 8
Unused termination
HR
Do not connect.
Do not connect.
Do not connect.
and may be found in
of the Timing Diagrams.
A
via 1kΩ resistor.
FIGURE 19. AutoSync Example
OD
AD
minus
adjust
Table
Table
46
17.4.1 AutoSync Feature
AutoSync is a new feature which continuously synchronizes
the outputs of multiple ADC12D800/500RFs in a system. It
may be used to synchronize the DCLK and data outputs of
one or more Slave ADC12D800/500RFs to one Master
ADC12D800/500RF. Several advantages of this feature in-
clude: no special synchronization pulse required, any upset
in synchronization is recovered upon the next DCLK cycle,
and the Master/Slave ADC12D800/500RFs may be arranged
as a binary tree so that any upset will quickly propagate out
of the system.
An example system is shown below in
sists of one Master ADC and two Slave ADCs. For simplicity,
only one DCLK is shown; in reality, there is DCLKI and
DCLKQ, but they are always in phase with one another.
held in a designated state (logic-high) in Demux Mode; in
Non-Demux Mode, the DCLK continues to function normally.
Depending upon when the DCLK_RST signal is asserted,
there may be a narrow pulse on the DCLK line during this
reset event. When the DCLK_RST signal is de-asserted,
there are t
next CLK rising edge synchronizes the DCLK output with
those of other ADC12D800/500RFs in the system. For 90°
Mode (DDRPh = logic-high), the synchronizing edge occurs
on the rising edge of CLK, 4 cycles after the first rising edge
of CLK after DCLK_RST is released. For 0° Mode (DDRPh =
logic-low), this is 5 cycles instead. The DCLK output is en-
abled again after a constant delay of t
For both Demux and Non-Demux Modes, there is some un-
certainty about how DCLK comes out of the reset state for the
first DCLK_RST pulse. For the second (and subsequent)
DCLK_RST pulses, the DCLK will come out of the reset state
in a known way. Therefore, if using the DCLK Reset feature,
it is recommended to apply one "dummy" DCLK_RST pulse
before using the second DCLK_RST pulse to synchronize the
outputs. This recommendation applies each time the device
or channel is powered-on.
When
ADC12D800/500RFs, it is required that the Select Phase bits
in the Control Register (Addr: Eh, Bits 3,4) be the same for
each Master ADC12D800/500RF.
using
SYNC_DLY
DCLK_RST
CLK cycles of systematic delay and the
to
synchronize
OD
Figure 19
.
30128603
which con-
multiple