adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 36

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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16.2.2 Extended Control Mode
In Extended Control Mode (ECM), most functions are con-
trolled via the Serial Interface. In addition to this, several of
the control pins remain active. See
is selected by setting the ECE Pin to logic-low. If the ECE Pin
is set to logic-high (Non-ECM), then the registers are reset to
their default values. So, a simple way to reset the registers is
by
ADC12D800/500RF control the Serial Interface: SCS, SCLK,
SDI and SDO. This section covers the Serial Interface. The
Register Definitions are located at the end of the datasheet
so that they are easy to find, see
nitions.
16.2.2.1 The Serial Interface
The ADC12D800/500RF offers a Serial Interface that allows
access to the sixteen control registers within the device. The
Serial Interface is a generic 4-wire (optionally 3-wire) syn-
chronous interface that is compatible with SPI type interfaces
that are used on many micro-controllers and DSP controllers.
Each serial interface access cycle is exactly 24 bits long. A
register-read or register-write can be accomplished in one
cycle. The signals are defined in such a way that the user can
opt to simply join SDI and SDO signals in his system to ac-
complish a single, bidirectional SDI/O signal. A summary of
the pins for this interface may be found in
ure 10
cation details. Control register contents are retained when the
device is put into power-down mode. If this feature is unused,
the SCLK, SDI, and SCS pins may be left floating because
they each have an internal pull-up.
SCS: Each assertion (logic-low) of this signal starts a new
register access, i.e. the SDI command field must be ready on
the following SCLK rising edge. The user is required to de-
assert this signal after the 24th clock. If the SCS is de-
asserted before the 24th clock, no data read/write will occur.
For a read operation, if the SCS is asserted longer than 24
clocks, the SDO output will hold the D0 bit until SCS is de-
toggling
for the timing diagram and
Pin
C4
C5
B4
A3
TABLE 18. Serial Interface Pins
the
ECE
SCS (Serial Chip Select bar)
SDO (Serial Data Out)
SCLK (Serial Clock)
SDI (Serial Data In)
pin.
Section 18.0 Register Defi-
Table 15
Table 20
Name
Four
FIGURE 11. Serial Data Protocol - Read Operation
Table
for timing specifi-
for details. ECM
pins
18. See
on
Fig-
the
36
asserted. For a write operation, if the SCS is asserted longer
than 24 clocks, data write will occur normally through the SDI
input upon the 24th clock. Setup and hold times, t
t
be toggled in between register access cycles.
SCLK: This signal is used to register the input data (SDI) on
the rising edge; and to source the output data (SDO) on the
falling edge. The user may disable the clock and hold it at
logic-low. There is no minimum frequency requirement for
SCLK; see f
SDI: Each register access requires a specific 24-bit pattern at
this input, consisting of a command field and a data field. If
the SDI and SDO wires are shared (3-wire mode), then during
read operations, it is necessary to tri-state the master which
is driving SDI while the data field is being output by the ADC
on SDO. The master must be tri-stated before the falling edge
of the 8
then this is not necessary. Setup and hold times, t
t
SDO: This output is normally tri-stated and is driven only
when SCS is asserted, the first 8 bits of command data have
been received and it is a READ operation. The data is shifted
out, MSB first, starting with the 8th clock's falling edge. At the
end of the access, when SCS is de-asserted, this output is tri-
stated once again. If an invalid address is accessed, the data
sourced will consist of all zeroes. If it is a read operation, there
will be a bus turnaround time, t
the command field was read in until the first bit of the data field
is written out.
Table 19
The serial data protocol is shown for a read and write opera-
tion in
HCS
SSU
Bit No.
9-24
2-3
4-7
1
8
, with respect to the SCLK must be observed.
, with respect to the SCLK must be observed. SCS must
TABLE 19. Command and Data Field Definitions
Figure 11
th
clock. If SDI and SDO are not shared (4-wire mode),
Read/Write (R/W)
shows the Serial Interface bit definitions.
SCLK
Reserved
D<15:0>
A<3:0>
Name
in
and
X
Table 15
Figure
16 registers may be addressed.
12, respectively.
for more details.
0b indicates a write operation
1b indicates a read operation
Data written to or read from
BSU
This is a "don't care" bit
Bits must be set to 10b
The order is MSB first
, from when the last bit of
addressed register
Comments
SCS
SH
30128692
and
and