adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 42

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

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device is powered-on, it can execute a calibration even
though the CAL Pin/Bit remains logic-low.
The power-on calibration will be not be performed if the CAL
pin is logic-high at power-on. In this case, the calibration cycle
will not begin until the on-command calibration conditions are
met. The ADC12D800/500RF will function with the CAL pin
held high at power up, but no calibration will be done and
performance will be impaired.
If it is necessary to toggle the CalDly Pin before the system
power up sequence, then the CAL Pin/Bit must be set to logic-
high during the toggling and afterwards for 10
Clock cycles. This will prevent the power-on calibration, so an
on-command calibration must be executed or the perfor-
mance will be impaired.
16.3.3.4 On-command Calibration
In addition to the power-on calibration, it is recommended to
execute an on-command calibration whenever the settings or
conditions to the device are altered significantly, in order to
obtain optimal parametric performance. Some examples in-
clude: changing the FSR via either ECM or Non-ECM, power-
cycling either channel, and switching into or out of DES Mode.
For best performance, it is also recommended that an on-
command calibration be run 20 seconds or more after appli-
cation of power and whenever the operating temperature
changes significantly, relative to the specific system perfor-
mance requirements.
Due to the nature of the calibration feature, it is recommended
to avoid unnecessary activities on the device while the cali-
bration is taking place. For example, do not read or write to
the Serial Interface or use the DCLK Reset feature while cal-
ibrating the ADC. Doing so will impair the performance of the
device until it is re-calibrated correctly. Also, it is recommend-
ed to not apply a strong narrow-band signal to the analog
inputs during calibration because this may impair the accu-
racy of the calibration; broad spectrum noise is acceptable.
16.3.3.5 Calibration Adjust
The sequence of the calibration event itself may be adjusted.
This feature can be used if a shorter calibration time than the
default is required; see t
mance of the device, when using this feature is not guaran-
teed.
The calibration sequence may be adjusted via CSS (Addr:
4h, Bit 14). The default setting of CSS = 1b executes both
R
Calibration (using Rext). Executing a calibration with CSS =
0b executes only the internal linearity Calibration. The first
time that Calibration is executed, it must be with CSS = 1b to
trim R
erating temperature and R
time, it will not drift significantly. To save time in subsequent
calibrations, trimming R
setting CSS = 0b.
16.3.3.6 Read/Write Calibration Settings
When the ADC performs a calibration, the calibration con-
stants are stored in an array which is accessible via the
Calibration Values register (Addr: 5h). To save the time which
it takes to execute a calibration, t
previous calibration result, these values can be read from and
written to the register at a later time. For example, if an ap-
plication requires the same input impedance, R
IN
and R
IN
and R
IN_CLK
IN_CLK
Calibration (using Rtrim) and internal linearity
. However, once the device is at its op-
IN
CAL
and R
IN
in
has been trimmed at least one
Table
IN_CLK
CAL
16. However, the perfor-
, or to allow re-use of a
may be skipped, i.e. by
IN
, this feature
9
Sampling
42
can be used to load a previously determined set of values.
For the calibration values to be valid, the ADC must be oper-
ating under the same conditions, including temperature, at
which the calibration values were originally determined by the
ADC.
To read calibration values from the SPI, do the following:
1. Set ADC to desired operating conditions.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Power down both I- and Q-channels.
4. Read exactly 184 times the Calibration Values register
(Addr: 5h). The register values are R0, R1, R2... R183 where
R0 is a dummy value. The contents of R<183:0> should be
stored.
5. Power up I- and Q-channels to original setting.
6. Set SSC (Addr: 4h, Bit 7) to 0.
7. Continue with normal operation.
To write calibration values to the SPI, do the following:
1. Set ADC to operating conditions at which Calibration Val-
ues were previously read.
2. Set SSC (Addr: 4h, Bit 7) to 1.
3. Power down both I- and Q-channels.
4. Write exactly 185 times the Calibration Values register (Ad-
dr: 5h). The registers should be written with stored register
values R1, R2... R183, dummy1, dummy2.
5. Power up I- and Q-channels to original setting.
6. Set SSC (Addr: 4h, Bit 7) to 0.
7. Continue with normal operation.
16.3.3.7 Calibration and Power-Down
If PDI and PDQ are simultaneously asserted during a cali-
bration cycle, the ADC12D800/500RF will immediately power
down. The calibration cycle will continue when either or both
channels are powered back up, but the calibration will be
compromised due to the incomplete settling of bias currents
directly after power up. Therefore, a new calibration should
be executed upon powering the ADC12D800/500RF back up.
In general, the ADC12D800/500RF should be recalibrated
when either or both channels are powered back up, or after
one channel is powered down. For best results, this should
be done after the device has stabilized to its operating tem-
perature.
16.3.3.8 Calibration and the Digital Outputs
During calibration, the digital outputs (including DI, DId, DQ,
DQd and OR) are set logic-low, to reduce noise. The DCLK
runs continuously during calibration. After the calibration is
completed and the CalRun signal is logic-low, it takes an ad-
ditional 60 Sampling Clock cycles before the output of the
ADC12D800/500RF is valid converted data from the analog
inputs. This is the time it takes for the pipeline to flush, as well
as for other internal processes.
16.3.4 Power Down
On the ADC12D800/500RF, the I- and Q-channels may be
powered down individually. This may be accomplished via the
control pins, PDI and PDQ, or via ECM. In ECM, the PDI and
PDQ pins are logically OR'd with the Control Register setting.
See
andSection 16.2.1.7 Power Down Q-channel Pin (PDQ)
more information.
Section 16.2.1.6 Power Down I-channel Pin (PDI)
for