adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 38

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

www.national.com
16.3 FEATURES
The ADC12D800/500RF offers many features to make the
device convenient to use in a wide variety of applications.
DDR Clock Phase Selection
Test Pattern Mode at Output
Power-on Calibration Delay
DDR / SDR DCLK Selection
Input Offset Adjust Setting
SDR Rising / Falling DCLK
DES Mode Input Selection
LVDS Differential Voltage
Demux/Non-Demux Mode
On-command Calibration
Input Full-scale Range
Sampling Clock Phase
AC/DC-coupled Mode
LVDS Common-Mode
DES / Non-DES Mode
Amplitude Selection
Selection
DES Timing Adjust
Selection
Selection
Voltage Amplitude
Output Formatting
DESCLKIQ Mode
DCLK Reset
Time Stamp
AutoSync
Selection
Selection
Selection
Selection
(Note
(Note
(Note
(Note
(Note
Feature
Adjust
Adjust
(Note
(Note
(Note
17)
17)
17)
17)
17)
17)
17)
17)
Selected via DDRPh
Selected via CalDly
Selected via V
Selected via NDM
Offset Binary only
Selected via FSR
Selected via DES
Selected via TPM
Selected via CAL
Higher amplitude
Selected via V
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Non-ECM
(Pin W4)
(Pin C2)
(Pin Y3)
(Pin V5)
(Pin B1)
(Pin A4)
(Pin A5)
(Pin D6)
(Pin V4)
only
TABLE 20. Features and Modes
CMO
BG
Output Control and Adjust
Input Control and Adjust
Active in ECM
Control Pin
Calibration
Yes
Yes
Yes
Yes
Yes
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
38
Table 20
details for the control mode chosen. "N/A" means "Not Appli-
cable."
Selected via the DES Timing
Selected via the Config Reg
Selected via the Config Reg
Selected via the Config Reg
Selected via the Config Reg
Selected via the Config Reg
Selected via the DEQ, DIQ
Selected via the DCK Bit
Selected via the SDR Bit
Selected via the OVS Bit
Selected via the TPM Bit
Selected via the DES Bit
Selected via the DPS Bit
Selected via the DPS Bit
Selected via the 2SC Bit
Selected via the TSE Bit
Selected via the CAL Bit
(Addr: 0h; Bits: 6:5)
(Addr: Ch and Dh)
(Addr: 3h and Bh)
(Addr: 2h and Ah)
(Addr: 0h; Bit: 14)
(Addr: 0h; Bit: 14)
(Addr: 0h; Bit: 13)
(Addr: 0h; Bit: 12)
(Addr: 0h; Bit: 15)
(Addr: Eh; Bit: 6)
(Addr: Eh; Bit: 0)
is a summary of the features available, as well as
(Addr: 0h; Bit: 7)
(Addr: 0h; Bit: 2)
(Addr: 0h; Bit: 4)
(Addr: 0h; Bit: 3)
Not available
Not available
Not available
Not available
Adjust Reg
(Addr: Eh)
(Addr: 7h)
ECM
Bits
DCLK Reset disabled
Time Stamp disabled
Default ECM State
RCOut1/2 disabled
t
AD
Higher amplitude
Non-DES Mode
Mid skew offset
Mid FSR value
Offset = 0 mV
TPM disabled
Master Mode,
Offset Binary
adjust disabled
DDR Mode
(CAL = 0)
0° Mode
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A