adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 45

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

The choice of capacitor value will depend on the clock fre-
quency, capacitor component characteristics and other sys-
tem economic factors. For example, on the ADC12D800R-
FRB, the capacitors have the value C
yields a highpass cutoff frequency, f
17.2.2 CLK Frequency
Although the ADC12D800/500RF is tested and its perfor-
mance is guaranteed with a differential 1.0/1.6 GHz sampling
clock, it will typically function well over the input clock fre-
quency range; see f
eration up to f
temperatures indicated are not exceeded. Operating at sam-
ple rates above f
ature may result in reduced device reliability and product
lifetime. This is due to the fact that higher sample rates results
in higher power consumption and die temperatures. If f
300 MHz, enable LFS in the Control Register (Addr: 0h, Bit
8).
17.2.3 CLK Level
The input clock amplitude is specified as V
10. Input clock amplitudes above the max V
in increased input offset voltage. This would cause the con-
verter to produce an output code other than the expected
2047/2048 when both input pins are at the same potential.
Insufficient input clock levels will result in poor dynamic per-
formance. Both of these results may be avoided by keeping
the clock input amplitude within the specified limits of
V
17.2.4 CLK Duty Cycle
The duty cycle of the input clock signal can affect the perfor-
mance of any A/D converter. The ADC12D800/500RF fea-
tures a duty cycle clock correction circuit which can maintain
performance over the 20%-to-80% specified clock duty-cycle
range. This feature is enabled by default and provides im-
proved ADC clocking, especially in the Dual-Edge Sampling
(DES) Mode.
17.2.5 CLK Jitter
High speed, high performance ADCs such as the
ADC12D800/500RF require a very stable input clock signal
with minimum phase noise or jitter. ADC jitter requirements
are defined by the ADC resolution (number of bits), maximum
ADC input frequency and the input signal amplitude relative
to the ADC input full scale range. The maximum jitter (the sum
of the jitter from all sources) allowed to prevent a jitter-induced
reduction in SNR is found to be
where t
V
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
analog input.
t
the jitter from all sources, including: the ADC input clock, sys-
tem, input signals and the ADC itself. Since the effective jitter
added by the ADC is beyond user control, it is recommended
to keep the sum of all other externally added jitter to a mini-
mum.
17.2.6 CLK Layout
The ADC12D800/500RF clock input is internally terminated
with a trimmed 100Ω resistor. The differential input clock line
pair should have a characteristic impedance of 100Ω and
J(MAX)
IN_CLK
IN(P-P)
IN
is the square root of the sum of the squares (RSS) of
.
is the maximum input frequency, in Hertz, at the ADC
t
J(MAX)
is the peak-to-peak analog input signal, V
J(MAX)
is the rms total of all jitter sources in seconds,
= ( V
CLK
CLK
(max) is possible if the maximum ambient
IN(P-P)
(max) for the maximum ambient temper-
CLK
(min) and f
/ V
FSR
) x (1/(2
CLK
c
= 677.2 kHz.
(max) in
(N+1)
couple
x
IN_CLK
= 4.7 nF which
π
IN_CLK
Table
x f
IN
may result
FSR
))
in
14. Op-
Table
is the
CLK
<
45
(when using a balun), be terminated at the clock source in that
(100Ω) characteristic impedance.
It is good practice to keep the ADC input clock line as short
as possible, tightly coupled, keep it well away from any other
signals, and treat it as a transmission line. Otherwise, other
signals can introduce jitter into the input clock signal. Also, the
clock signal can introduce noise into the analog path if it is not
properly isolated.
17.3 THE LVDS OUTPUTS
The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS.
The electrical specifications of the LVDS outputs are com-
patible with typical LVDS receivers available on ASIC and
FPGA chips; but they are not IEEE or ANSI communications
standards compliant due to the low +1.9V supply used on this
chip. These outputs should be terminated with a 100Ω differ-
ential resistor placed as closely to the receiver as possible. If
the 100Ω differential resistance is built in to the receiver, then
an externally placed resistor is not necessary. This section
covers common-mode and differential voltage, and data rate.
17.3.1 Common-mode and Differential Voltage
The LVDS outputs have selectable common-mode and dif-
ferential voltage, V
tion 16.3.2 Output Control and Adjust
Selecting the higher V
differential voltage, V
lower value. For short LVDS lines and low noise systems,
satisfactory performance may be realized with the lower
V
LVDS lines are long and/or the system in which the
ADC12D800/500RF is used is noisy, it may be necessary to
select the higher V
17.3.2 Output Data Rate
The data is produced at the output at the same rate it is sam-
pled at the input. The minimum recommended input clock rate
for this device is f
ble to operate the device in 1:2 Demux Mode and capture data
from just one 12-bit bus, e.g. just DI (or DId) although both DI
and DId are fully operational. This will decimate the data by
two and effectively halve the data rate.
17.3.3 Terminating Unused LVDS Output Pins
If the ADC is used in Non-Demux Mode, then only the DI and
DQ data outputs will have valid data present on them. The
DId and DQd data outputs may be left not connected; if un-
used, they are internally tri-stated.
Similarly, if the Q-channel is powered-down (i.e. PDQ is logic-
high), the DQ data output pins, DCLKQ and ORQ may be left
not connected.
17.4 SYNCHRONIZING MULTIPLE ADC12D800/500RFS
IN A SYSTEM
The ADC12D800/500RF has two features to assist the user
with synchronizing multiple ADCs in a system; AutoSync and
DCLK Reset. The AutoSync feature is new and designates
one ADC12D800/500RF as the Master ADC and other
ADC12D800/500RFs in the system as Slave ADCs. The
DCLK Reset feature performs the same function as the Au-
toSync feature, but is the first generation solution to synchro-
nizing multiple ADCs in a system; it is disabled by default. For
the application in which there are multiple Master and Slave
ADC12D800/500RFs in a system, AutoSync may be used to
synchronize the Slave ADC12D800/500RF(s) to each re-
spective Master ADC12D800/500RF and the DCLK Reset
OD
. This will also result in lower power consumption. If the
CLK(MIN)
OD
OS
.
OD
OS
and V
, may be selected for the higher or
; see
will also increase V
OD
Table
; see
14. However, it is possi-
for more information.
Table
OD
12. See
slightly. The
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Sec-