adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 41
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adc12d800rfrb
Manufacturer Part Number
adc12d800rfrb
Description
12-bit, 1.6/1.0 Gsps Rf Sampling Adc
Manufacturer
National Semiconductor Corporation
Datasheet
1.ADC12D800RFRB.pdf
(62 pages)
test pattern generator is connected to the outputs, including
ORI and ORQ. The test pattern output is the same in DES
Mode or Non-DES Mode. Each port is given a unique 12-bit
word, alternating between 1's and 0's. When the part is pro-
grammed into the Demux Mode, the test pattern’s order is
described in
the test pattern will not be output for that channel.
When the part is programmed into the Non-Demux Mode, the
test pattern’s order is described in
16.3.2.7 Time Stamp
The Time Stamp feature enables the user to capture the tim-
ing of an external trigger event, relative to the sampled signal.
When enabled via the TSE Bit (Addr: 0h; Bit: 3), the LSB of
the digital outputs (DQd, DQ, DId, DI) captures the trigger in-
formation. In effect, the 12-bit converter becomes an 11-bit
converter and the LSB acts as a 1-bit converter with the same
latency as the 11-bit converter. The trigger should be applied
to the DCLK_RST input. It may be asynchronous to the ADC
sampling clock.
Time
Time
T10 FF7h FEFh 008h 010h
T11 FF7h FEFh 008h 010h
T12 008h 010h FF7h FEFh
T13
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
FF7h FEFh 008h 010h
FF7h FEFh 008h 010h
FF7h FEFh 008h 010h
FF7h FEFh 008h 010h
008h 010h FF7h FEFh
008h 010h FF7h FEFh
008h 010h 008h 010h
008h 010h FF7h FEFh
008h 010h FF7h FEFh
008h 010h 008h 010h
TABLE 22. Test Pattern by Output Port in
TABLE 23. Test Pattern by Output Port in
Qd
...
FF7h
FF7h
FF7h
FF7h
FF7h
FF7h
008h
008h
008h
008h
008h
008h
008h
008h
Q
...
Table
Id
...
FEFh
FEFh
FEFh
FEFh
FEFh
FEFh
010h
010h
010h
010h
010h
010h
010h
010h
22. If the I- or Q-channel is powered down,
...
I
Non-Demux Mode
...
Q
Demux Mode
ORQ ORI
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
1b
...
...
I
0b
1b
0b
1b
0b
0b
1b
0b
1b
0b
0b
1b
0b
1b
...
ORQ ORI Comments
Table
1b
1b
1b
1b
0b
1b
1b
1b
1b
0b
1b
1b
1b
...
Pattern Sequence
Pattern Sequence
Pattern Sequence
23.
1b
1b
1b
1b
0b
1b
1b
1b
1b
0b
1b
1b
1b
...
Comments
n+1
n+2
Sequence
Sequence
Sequence
n
Pattern
Pattern
Pattern
n+1
n+2
n
41
16.3.3 Calibration Feature
The ADC12D800/500RF calibration must be run to achieve
specified performance. The calibration procedure is exactly
the same regardless of how it was initiated or when it is run.
Calibration trims the analog input differential termination re-
sistors, the CLK input resistor, and sets internal bias currents
which affect the linearity of the converter. This minimizes full-
scale error, offset error, DNL and INL, which results in the
maximum dynamic performance, as measured by: SNR,
THD, SINAD (SNDR) and ENOB.
16.3.3.1 Calibration Control Pins and Bits
Table 24
See
complete pin information and
16.3.3.2 How to Execute a Calibration
Calibration may be initiated by holding the CAL pin low for at
least t
another t
imum t
quired to ensure that random noise does not cause a
calibration to begin when it is not desired. The time taken by
the calibration procedure is specified as t
active in both ECM and Non-ECM. However, in ECM, the CAL
Pin is logically OR'd with the CAL Bit, so both the pin and bit
are required to be set low before executing another calibration
via either pin or bit.
16.3.3.3 Power-on Calibration
For standard operation, power-on calibration begins after a
time delay following the application of power, as determined
by the setting of the CalDly Pin and measured by t
Table
stabilize before the power-on calibration takes place. The
best setting (short or long) of the CalDly Pin depends upon
the settling time of the power supply.
It is strongly recommended to set CalDly Pin (to either logic-
high or logic-low) before powering the device on since this pin
affects the power-on calibration timing. This may be accom-
plished by setting CalDly via an external 1kΩ resistor con-
nected to GND or V
(Addr: 0h;
(Addr: 4h) Calibration Adjust
Pin (Bit)
Bit 15)
C1/D2
C3/D3
Section 9.0 Ball Descriptions and Equivalent Circuits
D6
V4
B5
CAL_L
16). This delay allows the power supply to come up and
CAL_L
is a summary of the pins and bits used for calibration.
CAL_H
clock cycles, and then holding it high for at least
and t
clock cycles, as defined in
(Input termination
TABLE 24. Calibration Pins
trim resistor)
(Calibration)
(Calibration
(Calibration
CAL_H
Reference
Running)
(External
Rtrim+/-
resistor)
CalRun
Rext+/-
CalDly
Delay)
Name
A
CAL
. If the CalDly Pin is toggled while the
input clock cycle sequences are re-
Figure 9
calibrate internal linearity
External resistor used to
External resistor used to
calibration is running
calibrate analog and
Initiate calibration
Adjust calibration
for the timing diagram.
Select power-on
calibration delay
Indicates while
CLK inputs
CAL
sequence
Table
Function
. The CAL Pin is
16. The min-
www.national.com
CalDly
(see
for