adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 49

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

from the ADC. Along with the ground plane, the parallel power
planes will provide additional thermal dissipation.
The center ground balls should be soldered down to the rec-
ommended ball pads (See AN-1126). These balls will have
wide traces which in turn have vias which connect to the in-
ternal ground planes, and a bottom ground pad/pour if pos-
sible. This ensures a good ground is provided for these balls,
and that the optimal heat transfer will occur between these
balls and the PCB ground planes.
In spite of these package enhancements, analysis using the
standard JEDEC JESD51-7 four-layer PCB thermal model
shows that ambient temperatures must be limited to 70/77°C
to ensure a safe operating junction temperature for the
ADC12D800/500RF. However, most applications using the
ADC12D800/500RF will have a printed circuit board which is
more complex than that used in JESD51-7. Typical circuit
boards will have more layers than the JESD51-7 (eight or
more), several of which will be used for ground and power
planes. In those applications, the thermal resistance param-
eters of the ADC12D800/500RF and the circuit board can be
used to determine the actual safe ambient operating temper-
ature up to a maximum of 85°C.
Three key parameters are provided to allow for modeling and
calculations. Because there are two main thermal paths be-
tween the ADC die and external environment, the thermal
resistance for each of these paths is provided. θ
the thermal resistance between the die and the exposed met-
al area on the top of the HSBGA package. θ
thermal resistance between the die and the center group of
balls on the bottom of the HSBGA package. The final param-
eter is the allowed maximum junction temperature, T
In other applications, a heat sink or other thermally conductive
path can be added to the top of the HSBGA package to re-
move heat. In those cases, θ
thermal parameters for the heat sink or other thermal coupling
added. Representative heat sinks which might be used with
the ADC12D800/500RF include the Cool Innovations p/n
3-1212XXG and similar products from other vendors. In many
applications, the printed circuit board will provide the primary
thermal path conducting heat away from the ADC package.
In those cases, θ
circuit board thermal modeling software to determine the al-
lowed operating conditions that will maintain the die temper-
ature below the maximum allowable limit. Additional dissipa-
tion can be achieved by coupling a heat sink to the copper
pour area on the bottom side of the printed circuit board.
Typically, dissipation will occur through one predominant
thermal path. In these cases, the following calculations can
be used to determine the maximum safe ambient operating
temperature for the ADC12D500RF, for example:
T
T
For θ
application environment should be used (θ
the thermal resistance from the case to ambient, which would
typically be that of the heat sink used. Using this relationship
and the desired ambient temperature, the required heat sink
thermal resistance can be found. Alternately, the heat sink
thermal resistance can be used to find the maximum ambient
J
J
= T
= T
JC
A
A
, the value for the primary thermal path in the given
+ P
+ P
D
C(MAX)
× (θ
JC
JC2
× (θ
+θ
can be used in conjunction with printed
CA
JC
+θ
)
CA
)
JC1
can be used along with the
JC1
JC2
or θ
represents the
JC1
represents
JC2
J
). θ
.
CA
is
49
temperature. For more complex systems, thermal modeling
software can be used to evaluate the printed circuit board
system and determine the expected junction temperature giv-
en the total system dissipation and ambient temperature.
17.6 SYSTEM POWER-ON CONSIDERATIONS
There are a couple important topics to consider associated
with the system power-on event including configuration and
calibration, and the Data Clock.
17.6.1 Power-on, Configuration, and Calibration
Following the application of power to the ADC12D800/500RF,
several events must take place before the output from the
ADC12D800/500RF is valid and at full performance; at least
one full calibration must be executed with the device config-
ured in the desired mode.
Following the application of power to the ADC12D800/500RF,
there is a delay of t
executed. This is why it is recommended to set the CalDly Pin
via an external pull-up or pull-down resistor. This ensures that
the state of that input will be properly set at the same time that
power is applied to the ADC and t
tity. For the purpose of this section, it is assumed that CalDly
is set as recommended.
The Control Bits or Pins must be set or written to configure
the ADC12D800/500RF in the desired mode. This must take
place via either Extended Control Mode or Non-ECM (Pin
Control Mode) before subsequent calibrations will yield an
output at full performance in that mode. Some examples of
modes include DES/Non-DES Mode, Demux/Non-demux
Mode, and Full-Scale Range.
The simplest case is when device is in Non-ECM and the
Control Pins are set by pull-up/down resistors, see
22. For this case, the settings to the Control Pins ramp con-
currently to the ADC voltage. Following the delay of t
the calibration execution time, t
ADC12D800/500RF is valid and at full performance. If it takes
longer than t
temperature, it is recommended to execute an on-command
calibration at that time.
Another case is when the FPGA configures the Control Pins
(Non-ECM) or writes to the SPI (ECM), see
always necessary to comply with the Operating Ratings and
Absolute Maximum ratings, i.e. the Control Pins may not be
driven below the ground or above the supply, regardless of
what the voltage currently applied to the supply is. Therefore,
it is not recommended to write to the Control Pins or SPI be-
fore power is applied to the ADC12D800/500RF. As long as
the FPGA has completed writing to the Control Pins or SPI,
the Power-on Calibration will result in a valid output at full
performance. Once again, if it takes longer than t
system to stabilize at its operating temperature, it is recom-
mended to execute an on-command calibration at that time.
Due to system requirements, it may not be possible for the
FPGA to write to the Control Pins or SPI before the Power-on
Calibration takes place, see
figure the device before the Power-on Calibration, but it is
critical to realize that the output for such a case is not at its
full performance. Following an On-command Calibration, the
device will be at its full performance.
CalDly
for the system to stabilize at its operating
CalDly
and then the Power-on Calibration is
Figure
CalDly
24. It is not critical to con-
CAL
, the output of the
will be a known quan-
Figure
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CalDly
CalDly
23. It is
Figure
for the
and