adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
adc12d800rfrb
Manufacturer Part Number
adc12d800rfrb
Description
12-bit, 1.6/1.0 Gsps Rf Sampling Adc
Manufacturer
National Semiconductor Corporation
Datasheet
1.ADC12D800RFRB.pdf
(62 pages)
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W19/W20
M18/M19
G19/G20
G17/G18
W18/V17
W17/V16
Y16/W16
W15/V15
Y14/W14
W13/V13
Y12/W12
W11/V11
Y10/W10
H19/H20
H17/H18
D19/D20
D18/E18
C19/C20
B18/C17
N19/N20
N17/N18
R18/R19
U19/U20
B17/C16
B15/C15
C14/D14
B13/C13
C12/D12
B11/C11
C10/D10
V14/U14
V12/U12
V10/U10
E19/E20
B19/B20
P19/P20
P17/P18
U18/T18
V19/V20
A18/A19
A16/B16
A14/B14
A12/B12
A10/B10
Y18/Y19
Ball No.
F18/F19
T19/T20
J18/J19
·
·
DQd11+/-
DQd10+/-
DId11+/-
DId10+/-
DQ11+/-
DQ10+/-
DQd9+/-
DQd8+/-
DQd7+/-
DQd6+/-
DQd5+/-
DQd4+/-
DQd3+/-
DQd2+/-
DQd1+/-
DQd0+/-
DI11+/-
DI10+/-
DId9+/-
DId8+/-
DId7+/-
DId6+/-
DId5+/-
DId4+/-
DId3+/-
DId2+/-
DId1+/-
DId0+/-
DQ9+/-
DQ8+/-
DQ7+/-
DQ6+/-
DQ5+/-
DQ4+/-
DQ3+/-
DQ2+/-
DQ1+/-
DQ0+/-
DI9+/-
DI8+/-
DI7+/-
DI6+/-
DI5+/-
DI4+/-
DI3+/-
DI2+/-
DI1+/-
DI0+/-
Name
·
·
Equivalent Circuit
15
Description
I- and Q-channel Digital Data Outputs. In Non-
Demux Mode, this LVDS data is transmitted at
the sampling clock rate. In Demux Mode, these
outputs provide ½ the data at ½ the sampling
clock rate, synchronized with the delayed data,
i.e. the other ½ of the data which was sampled
one clock cycle earlier. Compared with the DId
and DQd outputs, these outputs represent the
later time samples. If used, each of these outputs
should always be terminated with a 100Ω
differential resistor placed as closely as possible
to the differential receiver.
Delayed I- and Q-channel Digital Data Outputs.
In Non-Demux Mode, these outputs are tri-
stated. In Demux Mode, these outputs provide ½
the data at ½ the sampling clock rate,
synchronized with the non-delayed data, i.e. the
other ½ of the data which was sampled one clock
cycle later. Compared with the DI and DQ
outputs, these outputs represent the earlier time
samples. If used, each of these outputs should
always be terminated with a 100Ω differential
resistor placed as closely as possible to the
differential receiver.
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