adc12d800rfrb National Semiconductor Corporation, adc12d800rfrb Datasheet - Page 26

• Manufacturer Part Number: adc12d800rfrb
• Description: 12-bit, 1.6/1.0 Gsps Rf Sampling Adc
• Manufacturer: National Semiconductor Corporation

www.national.com
t
t
t
t
t
t
t
SCS
HCS
BSU
CAL
CAL_L
CAL_H
CalDly
TABLE 16. Calibration
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = GND
Note 3: When the input voltage at any pin exceeds the power supply limits, i.e. less than GND or greater than V
mA. In addition, over-voltage at a pin must adhere to the maximum voltage limits. Simultaneous over-voltage at multiple pins requires adherence to the maximum
package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on
specific customer thermal situation and specified package thermal resistances from junction to case.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω. Charged device model
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 6: The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this
device.
Note 7: To guarantee accuracy, it is required that V
Note 8: Typical figures are at T
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See
Specification Definitions for Gain Error.
Note 10: This parameter is guaranteed by design and is not tested in production.
Note 11: This parameter is guaranteed by design and/or characterization and is not tested in production.
Symbol
Symbol
SCS-to-Serial Clock Rising Setup
Time
SCS-to-Serial Clock Falling Hold
Time
Bus turn-around time
Calibration Cycle Time
CAL Pin Low Time
CAL Pin High Time
Calibration delay determined by
CalDly Pin
Parameter
Parameter
A
= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
A
, V
TC
, V
E
(Note
(Note
(Note
CalDly = Low
CalDly = High
and V
TC
= GND
DR
10)
10)
10)
be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.
DR
Conditions
Conditions
= GND
(Note
26
(Note
Figure
E
= 0V, unless otherwise specified.
10)
10)
3. For relationship between Gain Error and Full-Scale Error, see
30128604
ADC12D800RF ADC12D500RF
ADC12D800RF ADC12D500RF
2·10
Typ
Typ
2.5
1.5
10
7
A
, the current at that pin should be limited to 50
Lim
Lim
640
640
2
2
23
29
2·10
Typ
Typ
2.5
1.5
10
7
Lim
Lim
640
640
2
2
23
29
Sampling
Sampling
Sampling
(Limits)
(Limits)
Cycles
Cycles
Cycles
(max)
Units
Units
Clock
Clock
Clock
(min)
ns
ns
ns