adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 4

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adc1213d125hn/c1

Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Table 2.
Symbol
INBM
INBP
VDDA
VDDA
SCLK/DCS
SDIO/DCS
CS
AGND
RESET
SCRAMBLER
CFG0
CFG1
CFG2
CFG3
VDDD
DGND
DGND
DGND
VDDD
CMLPB
CMLNB
VDDD
DGND
DGND
VDDD
CMLNA
CMLPA
VDDD
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
SWING_0
SWING_1
DNC
VDDA
AGND
Pin description
All information provided in this document is subject to legal disclaimers.
Pin
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Rev. 05 — 23 April 2010
…continued
I
I
G
I
G
Type
P
P
I
I/O
I
I
I/O
I/O
I/O
I/O
P
G
G
G
P
O
O
P
G
G
P
O
O
P
G
G
I
I
G
P
I
I
O
P
[1]
Description
channel B complementary analog input
channel B analog input
analog power supply 3 V
analog power supply 3 V
chip select bar
analog ground
JEDEC digital IP reset
scrambler enable and disable
see
see
see
see
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
do not connect
analog power supply 3 V
analog ground
SPI clock
data format select
SPI data input/output
duty cycle stabilizer
Table 28
Table 28
Table 28
Table 28
ADC1213D series
(input) or OTRA (output)
(input) or OTRB (output)
(input)
(input)
ADC1213D series
© NXP B.V. 2010. All rights reserved.
[2]
[2]
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