adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 30

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 28.
[1]
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Table 29.
ADC1213D_SER_5
Preliminary data sheet
Bit
7 to 4
3 to 0
Bit
7
6
5
4
3
The default value for this register depends on the external pull-up/pull-down on CFG0, CFG1, CFG2 or CFG3. Writing to the register
overwrites this value.
F: number of byte per frame; HD: High density; K: number of frames per multi frame; M: number of converters; L: number of lanes
Symbol
-
CFG_SETUP[3:0]
Symbol
-
TRISTATE_CFG_PAD
SYNC_POL
SYNC_SINGLE_ENDED R/W
-
SER cfg set-up (address 0803h)
SER control1 (address 0805h)
See the information about the JESD204A standard on the JEDEC web site.
Access
R
R/W
R/W
R/W
Access
R
R
Value
0000
0000
(reset)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1101
1110
1111
All information provided in this document is subject to legal disclaimers.
[1]
Value
0
1
0
1
0
1
1
Rev. 05 — 23 April 2010
Description
not used
defines quick JESD204A configuration. These settings overrule the
CFG_PAD configuration
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2
ADC0: ON; ADC1: ON; Lane0: ON; Lane1: OFF; F = 4; HD = 0; K = 5;
M = 2; L = 1
ADC0: ON; ADC1: ON; Lane0: OFF
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: ON; F = 1; HD = 1; K = 17;
M = 1; L = 2; SWAP_ADC_0_1 = 1
ADC0: ON; ADC1: OFF; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1
ADC0: ON; ADC1: OFF; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_LANE_1_2 = 1
ADC0: OFF; ADC1: ON; Lane0: ON; Lane1: OFF; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1 = 1
ADC0: OFF; ADC1: ON; Lane0: OFF; Lane1: ON; F = 2; HD = 0; K = 9;
M = 1; L = 1; SWAP_ADC_0_1
reserved
ADC0: OFF; ADC1: OFF; Lane0: ON; Lane1: ON; F = 2; HD = 0; K = 9;
M = 2; L = 2; loop alignment = 1
ADC0: OFF; ADC1: OFF; Lane0: OFF; Lane1: OFF; F = 2; HD = 0;
K = 9; M = 2; L = 2 → PD
Description
not used
defines the sync signal polarity:
defines the input mode of the sync signal:
not used
CFG pads (3 to 0) are set to high-impedance. Switch to 0
automatically after start-up or reset.
synchronization signal is active low
synchronization signal is active high
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
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ADC1213D series
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ADC1213D series
© NXP B.V. 2010. All rights reserved.
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