adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 24

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
Fig 23. Transfer diagram for two data bytes (3-wire type)
SCLK
SDIO
CSB
R/W W1
14.6.2 Channel control
W0
A12 A11 A10
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
The steps involved in a data transfer are as follows:
The two ADC channels can be configured at the same time or separately. By using the
register “Channel index”, the user can choose which ADC channel will receive the next
SPI-instruction. By default the channel A and B will receive the same instructions in write
mode. In read mode only A is active.
1. The falling edge on CS in combination with a rising edge on SCLK determine the start
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can be vary in length but will
of communications.
always be a multiple of 8 bits. The MSB is always sent first (for instruction and data
bytes):
A9
Instruction bytes
A8
A7
A6
All information provided in this document is subject to legal disclaimers.
A5
A4
Rev. 05 — 23 April 2010
A3
A2
A1
A0
D7
D6
D5
Register N (data)
D4
D3
D2
ADC1213D series
D1
D0
D7
D6
D5
Register N + 1 (data)
D4
ADC1213D series
© NXP B.V. 2010. All rights reserved.
D3
D2
D1
005aaa086
D0
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