adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 25

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

Table 17.
Addr
Hex
ADC control register
0003
0005
0006
0008
0013
0014
0015
0016
JESD204A control
0801
0802
0803
0805
0806
0808
0809
080A
080B
0820
0821
0822
0823
0824
0825
Register name
Channel index
Reset and
Operating modes
Clock
Vref
Offset
Test pattern 1
Test pattern 2
Test pattern 3
Ser_Status
Ser_Reset
Ser_Cfg_Setup
Ser_Control1
Ser_Control2
Ser_Analog_Ctrl
Ser_ScramblerA
Ser_ScramblerB
Ser_PRBS_Ctrl
Cfg_0_DID
Cfg_1_BID
Cfg_3_SCR_L
Cfg_4_F
Cfg_5_K
Cfg_6_M
Register allocation map
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
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Bit definition
Bit 7
RXSYNC_
ERROR
SW_
SW_
SCR
RST
RST
0
0
0
0
0
0
0
0
0
0
-
-
-
-
Bit 6
CFG_PAD
TriState_
0
0
0
0
0
0
0
0
0
0
-
-
-
-
RESERVED[2:0]
RESERVED[2:0]
TESTPAT_3[5:0]
Bit 5
SYNC_
POL
0
0
0
0
0
0
0
0
0
0
-
-
-
RESERVED[5:0]
Bit 4
SYNC_SING
LEENDED
SE_SEL
0
0
0
0
0
0
0
0
0
-
-
TESTPAT_2[13:6]
MSB_INIT[7:0]
Bit 3
FSM_SW_
DIFF_SE
INTREF_
LSB_INIT[6:0]
RST
EN
DID[7:0]
0
1
0
0
0
0
0
0
-
DIG_OFFSET[5:0]
-
Bit 2
K[4:0]
0
0
0
0
0
0
-
-
-
CFG_SETUP[3:0]
BID[3:0]
Bit 1
SWING_SEL[2:0]
TESTPAT_1[2:0]
RESERVED[2:0]
LANE_1_2
CLKDIV2_
POR_TST
INTREF[2:0]
SWAP_
ADCB
SEL
F[2:0]
0
PRBS_TYPE[1:0]
0
0
-
PD[1:0]
Bit 0
RESERVED
ADC_0_1
DCS_EN
SWAP_
ADCA
M
0
L
-
Default
Bin
1111 1111
0000 0000
0000
000X
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 ****
0100 1001
0000 00**
0000 00**
0000 0000
1111 1111
0000 0000
1110 1101
0000 1010
*000 000*
0000 0***
000* ****
0000 000*
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