adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 29

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adc1213d125hn/c1

Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 25.
Table 26.
Table 27.
ADC1213D_SER_5
Preliminary data sheet
Bit
7 to 3
2 to 0
Bit
7
6 to 4
3 to 2
1
0
Bit
7
6 to 4
3
2 to 0
Symbol
TESTPAT_3[5:0]
-
Symbol
RXSYNC_ERROR
RESERVED[2:0]
-
POR_TST
RESERVED
Symbol
SW_RST
-
FSM_SW_RST
-
Register test pattern 3 (address 0016h)
SER status (address 0801h)
SER reset (address 0802h)
14.6.4 JESD204A digital control registers
Access
R/W
-
Access
R/W
-
-
R
-
Access
R/W
-
R/W
-
Value
00000
000
Value
0
010
0
1
-
Value
0
000
0
000
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
Description
custom digital test pattern (bit 5 to 0)
not used
Description
set to 1 when a synchronization error occurs
reserved
not used
power-on-reset
reserved
Description
initiates a software reset of the JEDEC204A unit
not used
initiates a software reset of the internal state machine of JEDEC204A
unit
not used
ADC1213D series
ADC1213D series
© NXP B.V. 2010. All rights reserved.
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