adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 18

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
14.2.4 Biasing
14.3.1 Drive modes
14.3 Clock input
The common-mode output voltage, V
common-mode input voltage, V
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
The ADC1213D can be driven differentially (SINE, LVPECL or LVDS) with little or no
influence on dynamic performances. It can also be driven by a single-ended LVCMOS
signal connected to pin CLKP (CLKM should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
Fig 16. LVCMOS single-ended clock input
a. Rising edge LVCMOS
0.1 μF
VCMA
VCMB
clock input
1.5 V
LVCMOS
All information provided in this document is subject to legal disclaimers.
PACKAGE
Rev. 05 — 23 April 2010
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CLKM
CLKP
I(cm)
ESD
, at the inputs to the sample and hold stage
O(cm)
PARASITICS
, should be set externally to 1.5 V (typical). The
b. Falling edge LVCMOS
ADC1213D series
COMMON MODE
REFERENCE
clock input
LVCMOS
ADC CORE
ADC1213D series
© NXP B.V. 2010. All rights reserved.
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CLKM
CLKP
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