adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 28

• Manufacturer Part Number: adc1213d125hn/c1
• Description: Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 21.
Table 22.
Table 23.
Table 24.
ADC1213D_SER_5
Preliminary data sheet
Bit
7 to 4 -
3
2 to 0 INTREF[2:0]
Register offset: (address 0013h)
Decimal
+31
...
0
...
−32
Bit
7 to 3
2 to 0
Bit
7 to 0
Symbol
INTREF_EN
Symbol
-
TESTPAT_1[2:0]
TESTPAT_2[13:6]
Symbol
Register Vref (address 0008h)
Digital offset adjustment (address 0013h)
Register test pattern 1 (address 0014h)
Register test pattern 2 (address 0015h)
Access
-
R/W
R/W
Access
-
R/W
Access
R/W
DIG_OFFSET[5:0]
011111
...
000000
...
100000
0000
Value
0
1
000
001
010
011
100
101
110
111
Value
00000
000
001
010
011
100
101
110
111
Value
00000000 custom digital test pattern (bit 13 to 6)
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
Description
not used
enable internal programmable VREF mode:
programmable internal reference:
Description
not used
digital test pattern:
Description
disable
active
0 dB (FS=2 V)
−1 dB (FS=1.78 V)
−2 dB (FS=1.59 V)
−3 dB (FS=1.42 V)
−4 dB (FS=1.26 V)
−5 dB (FS=1.12 V)
−6 dB (FS=1 V)
not used
off
mid-scale
− FS
+ FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern, to be written in register 0015h and 0016h
‘010101...’
‘101010...’
ADC1213D series
+31 LSB
...
0
...
−32 LSB
ADC1213D series
© NXP B.V. 2010. All rights reserved.
28 of 41