adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 27
adc1213d125hn/c1
Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
1.ADC1213D125HNC1.pdf
(41 pages)
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NXP Semiconductors
Table 18.
Table 19.
Table 20.
ADC1213D_SER_5
Preliminary data sheet
Bit
7 to 2
1
0
Bit
7
6 to 4
3 to 2
1 to 0
Bit
7 to 5
4
3
2
1
0
Symbol
RESERVED[5:0]
ADCB
ADCA
Symbol
SW_RST
RESERVED[2:0]
-
PD[1-0]
Symbol
-
SE_SEL
DIFF_SE
-
CLKDIV2_SEL
DCS_EN
Register channel Index (address 0003h)
Register reset and Power-down mode (address 0005h)
Register clock (address 0006h)
14.6.3.1 ADC control register
14.6.3 Register description
Access
-
R/W
R/W
Access
R/W
-
-
R/W
Access
-
R/W
R/W
-
R/W
R/W
Value
111111
0
1
0
1
Value
0
1
000
00
00
01
10
11
Value
000
0
1
0
1
0
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
Description
reserved
ADCB will get the next SPI command:
ADCA will get the next SPI command:
Description
reset digital part:
reserved
not used
power-down mode:
Description
not used
select SE clock input pin:
differential/single ended clock input select:
not used
select clock input divider by 2:
duty cycle stabilizer enable:
ADCB not selected
ADCB selected
ADCA not selected
ADCA selected
no reset
performs a reset of the digital part
normal (power-up)
full power-down
sleep
normal (power-up)
Select CLKM input
Select CLKP input
Fully differential
Single-ended
disable
active
disable
active
ADC1213D series
ADC1213D series
© NXP B.V. 2010. All rights reserved.
27 of 41
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