adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 23

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adc1213d125hn/c1

Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
14.6.1 Register description
14.6 Serial Peripheral Interface (SPI)
Table 13.
The ADC1213D serial interface is a synchronous serial communications port allowing for
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CS acts as the serial chip select bar.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see
Table 14.
[1]
Table 15.
[1]
Table 16.
INP-INM (V)
....
+0.9980469
+0.9985352
+0.9990234
+0.9995117
+1.0000000
> +1
Bit
Description
R/W
0
1
W1
0
0
1
1
R/W indicates whether a read or write transfer occurs after the instruction byte
Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
[1]
Table
Output codes versus input voltage
Instruction bytes for the SPI
Read or Write mode access description
Number of bytes to be transferred
14).
Offset binary
....
1111 1111 1011
1111 1111 1100
1111 1111 1101
1111 1111 1110
1111 1111 1111
1111 1111 1111
All information provided in this document is subject to legal disclaimers.
Description
Write mode operation
Read mode operation
MSB
7
R/W
A7
[1]
Rev. 05 — 23 April 2010
6
W1
A6
W0
0
1
0
1
5
W0
A5
…continued
4
A12
A4
Two’s complement
....
0111 1111 1011
0111 1111 1100
0111 1111 1101
0111 1111 1110
0111 1111 1111
0111 1111 1111
ADC1213D series
3
A11
A3
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 or more bytes transferred
2
A10
A2
ADC1213D series
© NXP B.V. 2010. All rights reserved.
1
A9
A1
LSB
0
A8
A0
23 of 41
OTR
0
0
0
0
0
0
1

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