adc1213d125hn/c1 NXP Semiconductors, adc1213d125hn/c1 Datasheet - Page 19

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adc1213d125hn/c1

Manufacturer Part Number
adc1213d125hn/c1
Description
Dual 12-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
ADC1213D_SER_5
Preliminary data sheet
14.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
Single-ended or differential clock inputs can be selected via the SPI (see
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
Fig 17. Differential clock input
Fig 18. Equivalent input circuit
a. Sine clock input
c. LVDS clock input
clock input
CLKM
CLKP
clock input
LVDS
Sine
All information provided in this document is subject to legal disclaimers.
Package
Rev. 05 — 23 April 2010
005aaa173
CLKM
CLKP
005aaa055
CLKM
CLKP
ESD
Parasitics
clock input
b. Sine clock input (with transformer)
d. LVPECL clock input
ADC1213D series
Sine
clock input
SE_SEL
Figure
LVPECL
5 kΩ
V
cm(clk)
18. The common-mode
SE_SEL
5 kΩ
ADC1213D series
© NXP B.V. 2010. All rights reserved.
005aaa172
005aaa081
CLKM
CLKP
Table
005aaa054
CLKM
CLKP
20). If
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