IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 55

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

D[39:0]
NOTES:
1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. REN and WEN must be held HIGH during this interval.
2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.
3. Setup and configuration static inputs are not affected during power down.
4. Serial programming and JTAG programming port are inactive during power down.
5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.
6. All flags remain active and maintain their current states.
7. During power down, all outputs will be in high-impedance.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
Q[39:0]
WCLK
ERCLK
RCLK
WEN
REN
EREN
PD
All input and output signals will also resume after this time period.
W
D1
t
DS
W
D10
t
t
A
ERCLK
W
t
DH
D2
t
DS
t
W
A
D11
W
D3
t
DH
t
A
W
D4
(1)
1
t
EREN
Figure 35. Power Down Operation
2
™
55
DDR/SDR FIFO
3
4
t
PDHZ
(7)
Hi-Z
t
PDL
COMMERCIAL AND INDUSTRIAL
Hi-Z
Hi-Z
t
PDLZ
t
TEMPERATURE RANGES
PDH
1ns
(2)
(2)
FEBRUARY 11, 2009
t
W
PDH
W
t
DS
DH
D12
(2)
t
DH
t
DS
W
t
A
6158 drw40
t
EREN
D13
W
DS