IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 10

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
SET-UP, CONFIGURATION & RESET PINS
must be always be used. These inputs must be set-up with respect to master
reset as they are latched during this time.
WDDR – Write Port DDR/SDR selection
RDDR – Read Port DDR/SDR selection
MD – Mode Selection
OW – Output width
IW – Input Width
FSEL[1:0] – Flag offset default values
IOSEL – I/O Level Selection
PFM – Programmable Flag Mode
FWFT/SI – First word Fall Through or IDT Standard mode
QUAD MODE
by the user:
INPUTS:
WCLK0, WCLK1, WCLK2, WCLK3 – Four write port clocks
WEN0, WEN1, WEN2, WEN3 – Four write port enables
WCS0, WCS1, WCS2, WCS3 – Four write port chip selects
RCLK0, RCLK1, RCLK2, RCLK3 – Four read port clocks
REN0, REN1, REN2, REN3 – Four read port enables
RCS0, RCS1, RCS2, RCS3, – Four read port chip selects
OE0, OE1, OE2, OE3 – Four read port output enables
OUTPUTS:
ERCLK0, ERCLK1, ERCLK2, ERCLK3 – Four read port echo read clocks
EREN0, EREN1, EREN2, EREN3 – Four read port echo read enables
EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port Empty/Output
Ready Flags
FF0/IR0, FF1/IR1, FF2/IR2, FF3/IR3 – Four write port full/ input ready flags
PAE0, PAE1, PAE2, PAE3 – Four read port programmable almost empty flags
PAF0, PAF1, PAF2, PAF3 – Four write port programmable almost empty flags
Regardless of the mode of operation, (Quad or Dual), the following inputs
The following inputs/ outputs should be used when Mux mode is selected
QUAD/DUAL I/O USAGE SUMMARY
™
10
DDR/SDR FIFO
DUAL MODE
by the user:
INPUTS:
WCLK0, WCLK2 – Two write port clocks
WEN0, WEN2 – Two write port enables
WCS0, WCS2 – Two write port chip selects
RCLK0, RCLK2 – Two read port clocks
REN0, REN2 – Two read port enables
RCS0, RCS2 – Two read port chip selects
OE0, OE2 – Two read port output enables
OUTPUTS:
ERCLK0, ERCLK2 – Two read port echo read clock outputs
EREN0, EREN2 – Two read port echo read enable outputs
EF0/OR0, EF2/OR2 – Two read port empty/output ready flags
FF0/IR0, FF2/IR2 – Two write port Full/ Input Ready Flags
PAE0, PAE2 – Two read port programmable almost empty flags
PAF0, PAF2 – Two write port programmable almost full flags
SERIAL PORT
Flag offsets is required:
SCLK – Serial Clock
SWEN – Serial Write Enable
SREN – Serial Read Enable
FWFT/SI – Serial Data In
SDO – Serial Data Out
The following inputs/ outputs should be used when Mux mode is selected
The following pins are used when user programming of the Programmable
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009