IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 18

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

SERIAL WRITING AND READING OF OFFSET REGISTERS
programmed with a specific value. One of four default values are loaded based
on the state of the FSEL[1:0] inputs. The flag offset values can be programmed
either through the dedicated serial programming port or the JTAG port. The
dedicated serial port can be used to load or read the contents of the offset
registers. The offset registers are programmed and read sequentially through
a series of shift registers. Each bit in the serial input will shift through the offset
registers and program each FIFOs offset registers.
FWFT/SI, SWEN , SREN and SDO pins. The total number of bits required per
device are listed in Figure 3, Programmable Flag Offset Programming
Methods. These bits account for all four PAE/PAF offset registers in the device.
To write to the offset registers, set the serial write enable signal active (LOW),
and on each rising edge of SCLK one bit from the FWFT/SI pin is serially shifted
into the flag offset register chain. Once the complete number of bits has been
programmed into all four registers, the programming sequence is complete. The
programming sequence is listed in Figure 3. To read the values from the offset
registers, set the serial read enable active (LOW). Then on each rising edge
of SCLK, one bit is shifted out to the serial data output. The serial read enable
must be kept LOW throughout the entire read operation. To stop reading the offset
register, disable the serial read enable (HIGH). There is a setup time for reading
PROGRAMMING INSTRUCTIONS:
JTAG Programming
1. Load JTAG Instruction code in "JTAG Timing Specifications" section.
2. Use rising edge of TCK to clock in the required bits from the TD2 input or to clock out from the TDO output pin.
Serial Programming
1. Set SWEN and SREN as shown above.
2. If reading, SREN LOW will clock data out of the SDO pin on every rising TCK edge. If writing, SWEN LOW will clock in data from the FWFT/SI pin.
NOTES:
1. The programming methods apply to both IDT Standard mode and FWFT mode.
2. The number of bits indicated are for all four PAE/PAF offset registers.
3. SWEN = 0, and SREN = 0 simultaneously are not allowed.
4. In Dual mode (IW/OW = x10), the total number of bits required will be half since only two FIFOs are active.
5. Parallel programming is not available.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
The offset registers can be loaded with a default value or they can be user
The serial read and write operations are performed by the dedicated SCLK,
JTAG Programming
Instruction Code
0008 (Hex)
0007 (Hex)
Serial Programming
SWEN
Figure 3. Programmable Flag Offset Programming Methods
0
1
SREN
1
0
IDT Part Number
IDT72T54242
IDT72T54252
IDT72T54262
IDT72T54242
IDT72T54252
IDT72T54262
™
18
DDR/SDR FIFO
the offset registers, as the offset register data for each FIFO is temporarily stored
in a scan chain. When data has been completely read out of the offset registers,
any additional read operations to the offset register will result in zeros as the
output data.
JTAG port. To write to the offset registers using JTAG, set the instructional register
to the offset write command (Hex Value = 0x0008). The JTAG port will load data
into each of the offset registers in a similar fashion as the serial programming
described above. To read the values from the offset registers, set the instructional
register to the offset read command (Hex Value = 0x0007). The TDO of the JTAG
port will output data in a similar fashion as the serial programming described
above.
size of the device selected and the width of the I/Os selected. Each offset register
requires 15 bits, 16 bits or 17 bits for the IDT72T54242/72T54252/72T54262
devices respectively. So a total of 120 bits, 128 bits or 136 bits will need to be
loaded into each offset register chain for the IDT72T54242/72T54252/72T54262
devices respectively. If Dual mode is selected, only two of the four offset register
will need to be programmed (PAE/PAF2, PAE/PAF0). Therefore, the total
number of bits required will be half of its Quad mode operation. See Figure 4,
Offset Register Serial Bit Sequence for a mapping of the serial bits to each offset
registers.
Reading and writing the offset registers can also be accomplished using the
The number of bits required to load the offset registers is dependent on the
Quad Mode
120
128
136
120
128
136
Dual Mode
(IW/OW = x10)
60
64
68
60
64
68
(4)
COMMERCIAL AND INDUSTRIAL
Dual Mode
(IW/OW = x20)
TEMPERATURE RANGES
56
60
64
56
60
64
6158 drw07
FEBRUARY 11, 2009