IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 33

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IDT72T54262L6-7BB

Manufacturer Part Number
IDT72T54262L6-7BB
Description
IC FIFO DDR/SDR QUAD/DUAL 324BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Tr
Datasheet

Specifications of IDT72T54262L6-7BB

Function
Asynchronous
Memory Size
5.2K (262 x 20)
Access Time
3.8ns
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
324-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72T54262L6-7BB

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72T54262L6-7BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72T54262L6-7BBI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. OE can be toggled during master reset. During master reset, the high-impedance control of the Qn data outputs are provided by OE only.
2. RCLK(s), WCLK(s) and SCLK(s) can be free running or idle.
3. The state of these pins are latched when the master reset pulse is LOW.
4. JTAG flag should not toggle during master reset.
5. RCS and WCS can be HIGH or LOW until the first rising edge of RCLK after master reset is complete.
6. If Dual mode is selected, only the signals designated with a "0" or "2" are used.
7. If Dual mode is selected, outputs Q[19:10] and Q[39:30] are not used if outputs are configured to x10.
WEN0/1/2/3
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
REN0/1/2/3
FSEL[1:0]
FWFT/SI
Q[39:0]
RDDR
WDDR
EF/OR
IOSEL
SWEN,
FF/IR
0/1/2/3
0/1/2/3
0/1/2/3
0/1/2/3
PFM
SREN
PAE
OW
PAF
MRS
MD
IW
(3)
(3)
(6)
(6)
(3)
(3)
(3)
(3)
(3)
(6)
(6)
(6)
(6)
(7)
(3)
(3)
,
,
t
t
t
t
t
t
t
t
RSS
RSS
t
RSS
RSS
RSS
RSS
RSS
RSS
RSS
t
t
t
t
t
RSF
RSF
RSF
RSF
RSF
HIGH = Quad mode
HIGH = Synchronous PAE/PAF Timing
HIGH = Read/Write Double Data Rate
LOW = Dual mode
LOW = Asynchronous PAE/PAF Timing
HIGH = FWFT Mode
HIGH = HSTL I/Os
LOW = Read/Write Single Data Rate
LOW = IDT Standard Mode
LOW = LVTTL I/Os
Figure 10 . Master Reset Timing
t
RS
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
33
DDR/SDR FIFO
OE = HIGH
OE = LOW
t
t
RSR
RSR
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 11, 2009
6158 drw15

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