IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 53

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

WCLK0
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. m0 = PAF0 offset .
2. D = maximum FIFO depth. For density of FIFO with bus-matching, refer to the bus-matching section on page 19.
4. t
5. PAF0 is asserted and updated on the rising edge of WCLK0 only.
6. RCS0 = LOW, and WCS0 = LOW.
7.
WCLK0
NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. n0 = PAE0 offset.
3. For IDT Standard mode
4. For FWFT mode.
5. t
6. PAE0 is asserted and updated on the rising edge of RCLK0 only.
7. RCS0 = LOW, and WCS0 = LOW.
8.
RCLK0
RCLK0
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
WEN0
WEN0
REN0
REN0
PAF0
PAE0
the rising edge of WCLK0 and the rising edge of RCLK0 is less than t
between the rising edge of RCLK0 and the rising edge of WCLK0 is less than t
SKEW3
SKEW3
MD
MD
1
1
Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE0 will go HIGH (after one RCLK0 cycle plus t
is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus t
Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)
D/C
D/C
IW
IW
t
CLKH
t
CLKL
D/C
OW
D/C
OW
t
ENS
t
t
ENS
CLKL
n0 words in FIFO
n0 + 1 words in FIFO
t
CLKL
WDDR
WDDR
0
0
D - (m0 +1) words in FIFO
t
RDDR
RDDR
ENH
t
SKEW3
(3)
1
0
0
t
ENH
,
(4)
(5)
PFM
PFM
1
1
t
PAES
1
(2)
2
SKEW3
, then the PAE0 deassertion may be delayed one extra RCLK0 cycle.
SKEW2
™
2
53
DDR/SDR FIFO
, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.
t
PAFS
t
ENS
t
ENS
n0 + 1 words in FIFO
n0 + 2 words in FIFO
t
ENH
t
SKEW3
D - m0 words in FIFO
t
ENH
(3)
(4)
(4)
,
1
1
COMMERCIAL AND INDUSTRIAL
(2)
t
PAES
TEMPERATURE RANGES
2
FEBRUARY 11, 2009
2
PAES
t
PAFS
). If the time between
PAFS
n0 words in FIFO
n0 + 1 words in FIFO
). If the time
D-(m0+1) words
in FIFO
6158 drw37
6158 drw36
(2)
(3)
,
(4)