IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 50

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

NOTE:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.
2. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS0 and OE0 are both active, LOW, that is the bus is not in High-
3. OE0 is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR0 is HIGH.
c.
d .
e.
f.
g .
h .
i .
4. OE0 is LOW, WDDR = LOW, and RDDR = LOW.
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
ERCLK0
WCLK0
RCLK0
EREN0
Impedance state.
WEN0
Q[9:0]
D[9:0]
REN0
RCS0
OR0
Reg.
O/P
RCS0 and REN0 are both disabled, the output bus is High-Impedance.
Word Wn+1 falls through to the output register, OR0 goes active, LOW.
RCS0 is HIGH, therefore the Qn outputs are High-Impedance. EREN0 goes LOW to indicate that a new word has been placed on the output register.
EREN0 goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS0 active LOW at least one cycle ahead of REN0, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
REN0 goes active LOW, this reads out the second word, Wn+2.
EREN0 goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN0 remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR0 flag goes HIGH and EREN0 goes HIGH to indicate that there is no new word available.
HIGH-Z
t
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR)
ENS
t
DS
W
t
ERCLK
n+1
W
t
DH
n
t
Last Word
SKEW1
t
DS
a
W
n+2
t
DH
1
b
t
DS
W
n+3
t
DH
2
t
ENH
c
t
t
t
REF
CLKEN
A
™
d
50
DDR/SDR FIFO
t
CLKEN
e
W
n+1
t
ENS
f
t
RCSLZ
t
ENS
W
n+1
g
t
t
t
COMMERCIAL AND INDUSTRIAL
A
A
CLKEN
W
W
n+2
n+2
TEMPERATURE RANGES
h
t
t
A
A
FEBRUARY 11, 2009
W
W
i
n+3
t
n+3
ENH
t
t
REF
CLKEN
6158 drw32