IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 4

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

DESCRIPTION
devices are ideal for many applications where data stream convergence and
parallel buffering of multiple data paths are required. These applications may
include communication systems such as data bandwidth aggregation, data
acquisition systems and medical equipment, etc. The Quad/Dual FIFO allows
the user to select either two or four individual internal FIFOs for operation. Each
internal FIFO has its own discrete read and write clock, independent read and
write enables, and separate status flags. The density of each FIFO is fixed.
and four write clocks. Data can be written into any of the four write ports totally
independent of any other port, and can be read out of any of the four read ports
corresponding to their respective write port. Each port has its own control
enables and status flags and is 10 bits wide. The device functions as four
separate 10-bit wide FIFOs.
and two write clocks. Data can be written into any of the two write ports totally
independent of any other port, and can be read out of any of the two read ports
corresponding to their respective write port. Each port has its own control
enables and status flags. All input and output ports have bus-matching
capabilities of x10 or x20 bits wide.
Standard mode and First Word Fall Through (FWFT) mode. This affects the
device operation and also the flag outputs. The device provides eight flag outputs
per input and output port. A dedicated Serial Clock is used for programming the
flag offsets. This clock is also used for reading the offset values. The serial read
and write operations are performed via the SCLK, FWFT/SI, SWEN, SREN,
and SDO pins. The flag offsets can also be programmed using the JTAG port.
If this option is selected, the SCLK, SWEN, and SREN pins must be disabled.
selectable SDR or DDR data transfer modes for the inputs and outputs. In SDR
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
The IDT72T54242/72T54252/72T54262 Quad/Dual TeraSync FIFO
If Quad mode is selected, there will be a total of eight clock domains, four read
If Dual mode is selected, there will be a total of four clock domains, two read
As typical with most IDT FIFOs, two types of data transfer are available, IDT
The Quad/Dual device offers a maximum throughput of 2Gbps per port, with
™
4
DDR/SDR FIFO
mode, the input clock can operate up to 200MHz. Data will transition/latch on
the rising edge of the clock. In DDR mode, the input clock can operate up to 100
MHz, with data transitioning/latched on both rising and falling edges of the clock.
The advantage of DDR is that it can achieve the same throughput as SDR with
only half the number of bits, assuming the frequency is constant. For example,
a 4Gbps throughput in SDR is 100MHz x 40 bits. In DDR mode, it is 100MHz
x 20 bits, because two bits transition per clock cycle.
and Echo Read Clock, ERCLK output. These outputs aid in high speed
applications where synchronization of the input clock and data of receiving
device is critical. Otherwise known as “Source Synchronous Clocking,” the
echo outputs provide tighter synchronization of the data transmitted from the
FIFO and the read clock interfacing the FIFO outputs.
latched with respect to a Master Reset pulse. For example, the mode of
operation, bus-matching, and data rate are selected at Master Reset. A Partial
Reset is provided for each internal FIFO. When a Partial Reset is performed
on a FIFO the read and write pointers of that FIFO are reset to the first memory
location. The flag offset values, timing modes, and initial configurations are
retained.
LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input
is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the
IOSEL pin. The core supply voltage of the device, V
the output pins have a separate supply, V
The inputs of this device are 3.3V tolerant when V
also offers significant power savings, most notably achieved by the presence
of a Power Down input, PD.
Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
All Read ports provide the user with a dedicated Echo Read Enable, EREN
A Master Reset input is provided and all setup and configuration pins are
The Quad/Dual device has the capability of operating its I/O at either 2.5V
A JTAG test port is provided. The Quad/Dual device has a fully functional
COMMERCIAL AND INDUSTRIAL
DDQ
which can be 2.5V, 1.8V, or 1.5V.
TEMPERATURE RANGES
DDQ
CC
FEBRUARY 11, 2009
is set to 2.5V. The device
is always 2.5V, however