IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 41

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

NOTES:
1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.
2. t
3. First data word latency = t
4. RCS0 = LOW.
5. RCLK0 must be free running for EF0 to update.
6.
WCLK0
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
RCLK0
WEN0
WCS0
REN0
Q[9:0]
D[9:0]
the rising edge of WCLK0 and the rising edge of RCLK0 is less than t
OE0
SKEW1
EF0
MD
1
is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus t
t
ENS
D/C
IW
Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)
D/C
OW
t
t
OLZ
ENH
SKEW1
t
REF
t
A
t
OE
+ 1*T
WDDR
t
ENS
0
t
SKEW1
t
ENS
RCLK
t
DS
W
(2)
RDDR
+ t
X
0
REF.
NO OPERATION
t
t
DH
ENH
FWFT/SI
W
1
X-1
0
SKEW1
t
OHZ
t
t
DS
ENS
, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - T
W
X+1
NO OPERATION
™
t
41
t
ENH
DH
t
DDR/SDR FIFO
ENH
2
t
CLKH
t
REF
t
OE
t
CLK
t
CLKL
t
ENS
W
X-1
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t
FEBRUARY 11, 2009
ENS
REF
W
X
). If the time between
SKEW
measurement)..
t
REF
t
t
ENH
A
6158 drw23
W
X+1