IDT72T54262L6-7BB IDT, Integrated Device Technology Inc, IDT72T54262L6-7BB Datasheet - Page 17

• Manufacturer Part Number: IDT72T54262L6-7BB
• Description: IC FIFO DDR/SDR QUAD/DUAL 324BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T54262L6-7BB

• Function: Asynchronous
• Memory Size: 5.2K (262 x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T54262L6-7BB

FUNCTIONAL DESCRIPTION
MASTER RESET & DEVICE CONFIGURATION
this includes the following:
of the above modes are selected. A master reset comprises of pulsing the MRS
input pin from high to low for a period of time (t
held in their respective states. Table 1 summarizes the configuration modes
available during master reset. They are described as follows:
master reset, MD is HIGH then Quad mode is selected, if MD is LOW then Dual
mode is selected. In Quad mode four independent FIFOs are available, while
in Dual mode two independent FIFOs are available.
selected using the FWFT/SI input. If FWFT/SI is LOW during master reset then
IDT Standard mode is selected, if it is high then FWFT mode is selected. The
timing modes are described later in this section.
data rates are port selectable. This is a versatile feature that allows the user to
select either SDR or DDR on the write ports and/or read ports of all FIFOs using
the WDDR and RDDR inputs. If WDDR is LOW during master reset then the write
ports of all FIFOs will function in SDR mode; if it is high then the write ports will
be DDR mode. If RDDR is LOW during master reset then the read ports of all
TABLE 1 — DEVICE CONFIGURATION
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
FSEL[1:0]
During Master Reset the device configuration and settings are determined,
1. Quad or Dual mode
2. IDT Standard or First Word Fall Through (FWFT) flag timing mode
3. Single or Double Data Rates on both the Write and Read ports
4. Programmable flag mode, synchronous or asynchronous timing
5. Write and Read Port Bus Widths, x10 or x20 (in Dual mode only)
6. Default Offsets for the programmable flags, 7, 63, 127, or 1023
7. LVTTL or HSTL I/O selection
The state of the configuration inputs during master reset will determine which
Quad or Dual mode. This mode is selected using the MD input. If during
IDT Standard or FWFT mode. The two available flag timing modes are
Single Data Rate (SDR) or Double Data Rate (DDR). The input/output
FWFT/SI
WDDR
IOSEL
RDDR
PINS
PFM
MD
OW
IW
VALUES
00
01
10
11
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
0
Dual mode
Quad mode
IDT Standard mode
FWFT mode
Single Data Rate write port
Double Data Rate write port
Single Data Rate read port
Double Data Rate read port
Asynchronous operation of PAE and PAF outputs
Synchronous operation of PAE and PAF outputs
Write port is 10 bits wide
Write port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
Read port is 10 bits wide
Read port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
Programmable flag registers offset value = 7
Programmable flag registers offset value = 63
Programmable flag registers offset value = 127
Programmable flag registers offset value = 1023
All applicable I/Os (except CMOS) are LVTTL
All applicable I/Os (except CMOS) are HSTL/eHSTL
CONFIGURATION
RS
) with the configuration inputs
™
17
DDR/SDR FIFO
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. In default programming, the offset value selected applies to all internal FIFOs.
2. To program different offset values for each FIFO, serial programming must be used.
3. n is the offset value for PAE, m is the offset value for PAF.
FIFOs will function in SDR mode; if it is high then the read port will be DDR mode.
This feature is described in the Signal Descriptions section.
either synchronous or asynchronous timing mode. If the programmable flag
input, PFM is HIGH during master reset then all programmable flags will operate
in a synchronous manner, meaning the PAE flags are double buffered and
updated based on the rising edge of its respective read clocks. The PAF flags
are also double buffered and updated based on the rising edge of its respective
write clocks. If it is LOW then all programmable flags will operate in an
asynchronous manner, meaning the PAE and PAF flags are not double buffered
and will update through the internal counter after a nominal delay. This feature
is described in the Signal Descriptions section.
the read and write ports using the IW and OW inputs. If IW is LOW then the write
ports will be 10 bits wide, if IW is HIGH then the write ports will be 20 bits wide.
If OW is LOW then the read ports will be 10 bits wide, if OW is HIGH then the read
ports will be 20 bits wide. Note in Quad mode the inputs and outputs are always
10 bits wide regardless of the state of these pins. This feature is described in the
Signal Descriptions section.
programmed or they can be set to one of four default values during a master
reset. For default programming, the state of the FSEL[1:0] inputs during master
reset will determine the value. Table 2, Default Programmable offsets lists the
four offset values and how to select them. For programming the offset values to
a specific number, use the serial programming signals (SCLK, SWEN, SREN,
FWFT/SI) to load the value into the offset register. You may also use the JTAG
port on this device to load the offset value. Keep in mind that you must disable
the serial programming signals if you plan to use the JTAG port for loading the
offset values. To disable the serial programming signals, tie SCLK, SWEN,
SREN, and FWFT/SI to V
programming of the flag offset values is provided in the "Serial Write and Reading
of Offset Registers” section.
or 1.5V HSTL / 1.8V eHSTL levels. The state of the IOSEL input will determine
which I/O level will be selected. If IOSEL is HIGH then the applicable I/Os will
be 1.5V HSTL or 1.8V eHSTL, depending on the voltage level applied to V
and V
= 1.8V. If IOSEL is LOW then the applicable I/Os will be 2.5V LVTTL. As noted
in the Pin Description section, IOSEL is a CMOS input and must be tied to either
V
CC
Programmable Almost Empty/Full Flags. These flags can operate in
Selectable Bus Width. In Dual mode, the bus width can be selected on
Programmable Flag Offset Values. These offset values can be user
I/O Level Selection. The I/Os can be selected for either 2.5V LVTTL levels
or GND for proper operation.
REF
FSEL1
. For HSTL, VDDQ and V
0
0
1
1
CC
IDT72T54242
IDT72T54252
IDT72T54262
. A thorough explanation of the serial and JTAG
FSEL0
REF
0
1
0
1
COMMERCIAL AND INDUSTRIAL
= 1.5V and for eHSTL VDDQ and V
TEMPERATURE RANGES
FEBRUARY 11, 2009
Offsets n,m
1023
127
63
7
DDQ
REF